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| author | Evgeny Stupachenko <evstupac@gmail.com> | 2014-06-05 10:26:18 +0000 |
|---|---|---|
| committer | Kirill Yukhin <kyukhin@gcc.gnu.org> | 2014-06-05 10:26:18 +0000 |
| commit | edbb07490964faff304b02ca854fc49adea81e54 (patch) | |
| tree | f2ff46659084837e30d6fabdd0b85affdb2ab6e9 | |
| parent | e12355efb750245dbf58be8b054f2ab360d53f9e (diff) | |
| download | gcc-edbb07490964faff304b02ca854fc49adea81e54.zip gcc-edbb07490964faff304b02ca854fc49adea81e54.tar.gz gcc-edbb07490964faff304b02ca854fc49adea81e54.tar.bz2 | |
sse.md (*ssse3_palignr<mode>_perm): New.
gcc/
* config/i386/sse.md (*ssse3_palignr<mode>_perm): New.
* config/i386/predicates.md (palignr_operand): New.
Indicates if permutation is suitable for palignr instruction.
From-SVN: r211264
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/predicates.md | 16 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 29 |
3 files changed, 51 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 98d56a5..6167424 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2014-06-05 Evgeny Stupachenko <evstupac@gmail.com> + + * config/i386/sse.md (*ssse3_palignr<mode>_perm): New. + * config/i386/predicates.md (palignr_operand): New. + Indicates if permutation is suitable for palignr instruction. + 2014-06-05 Yuri Rumyantsev <ysrumyan@gmail.com> PR tree-optimization/61319 diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index efc3a09..300c168 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1425,6 +1425,22 @@ return true; }) +;; Return true if OP is a parallel for a palignr permute. +(define_predicate "palignr_operand" + (and (match_code "parallel") + (match_code "const_int" "a")) +{ + int elt = INTVAL (XVECEXP (op, 0, 0)); + int i, nelt = XVECLEN (op, 0); + + /* Check that an order in the permutation is suitable for palignr. + For example, {5 6 7 0 1 2 3 4} is "palignr 5, xmm, xmm". */ + for (i = 1; i < nelt; ++i) + if (INTVAL (XVECEXP (op, 0, i)) != ((elt + i) % nelt)) + return false; + return true; +}) + ;; Return true if OP is a proper third operand to vpblendw256. (define_predicate "avx2_pblendw_operand" (match_code "const_int") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index c91626b..d9073535 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -14551,6 +14551,35 @@ (set_attr "prefix" "vex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "*ssse3_palignr<mode>_perm" + [(set (match_operand:V_128 0 "register_operand" "=x,x") + (vec_select:V_128 + (match_operand:V_128 1 "register_operand" "0,x") + (match_parallel 2 "palignr_operand" + [(match_operand 3 "const_int_operand" "n, n")])))] + "TARGET_SSSE3" +{ + enum machine_mode imode = GET_MODE_INNER (GET_MODE (operands[0])); + operands[2] = GEN_INT (INTVAL (operands[3]) * GET_MODE_SIZE (imode)); + + switch (which_alternative) + { + case 0: + return "palignr\t{%2, %1, %0|%0, %1, %2}"; + case 1: + return "vpalignr\t{%2, %1, %1, %0|%0, %1, %1, %2}"; + default: + gcc_unreachable (); + } +} + [(set_attr "isa" "noavx,avx") + (set_attr "type" "sseishft") + (set_attr "atom_unit" "sishuf") + (set_attr "prefix_data16" "1,*") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,vex")]) + (define_expand "avx_vinsertf128<mode>" [(match_operand:V_256 0 "register_operand") (match_operand:V_256 1 "register_operand") |