diff options
| author | Thomas Preud'homme <thomas.preudhomme@linaro.org> | 2018-12-19 15:01:41 +0000 |
|---|---|---|
| committer | Thomas Preud'homme <thopre01@gcc.gnu.org> | 2018-12-19 15:01:41 +0000 |
| commit | ec5e681485a3a069ccf0316dacba4ce6fa348c6b (patch) | |
| tree | f105c2e91ef6c469946b6d847eff2c2502d463cc | |
| parent | a152954ea4fee516e83b4f75a17818fbc8d555bb (diff) | |
| download | gcc-ec5e681485a3a069ccf0316dacba4ce6fa348c6b.zip gcc-ec5e681485a3a069ccf0316dacba4ce6fa348c6b.tar.gz gcc-ec5e681485a3a069ccf0316dacba4ce6fa348c6b.tar.bz2 | |
[ARM] Do softfloat when -mfpu set, -mfloat-abi=softfp
FP instructions are only enabled for TARGET_32BIT and TARGET_HARD_FLOAT
but GCC only gives an error when TARGET_HARD_FLOAT is true and -mfpu is
not set. Among other things, it makes some of the cmse tests (eg.
gcc.target/arm/cmse/baseline/softfp.c) fail when targeting
-march=armv8-m.base -mcmse -mfpu=<something> -mfloat-abi=softfp. This
commit adds an extra check for TARGET_32BIT to TARGET_HARD_FLOAT such
that it is false on TARGET_THUMB1 targets even when a FPU is specified.
2018-12-19 thomas Preud'homme <thomas.preudhomme@linaro.org>
gcc/
* config/arm/arm.h (TARGET_HARD_FLOAT): Restrict to TARGET_32BIT
targets.
* config/arm/arm.c (output_return_instruction): Only check
TARGET_HARD_FLOAT to decide whether FP instructions are available.
gcc/testsuite/
* gcc.target/arm/cmse/baseline/softfp.c: Force an FPU.
From-SVN: r267270
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/arm/arm.c | 2 | ||||
| -rw-r--r-- | gcc/config/arm/arm.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c | 4 |
5 files changed, 17 insertions, 3 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 597dca7..774c4f7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2018-12-19 Thomas Preud'homme <thomas.preudhomme@linaro.org> + + * config/arm/arm.h (TARGET_HARD_FLOAT): Restrict to TARGET_32BIT + targets. + * config/arm/arm.c (output_return_instruction): Only check + TARGET_HARD_FLOAT to decide whether FP instructions are available. + 2018-12-19 Tom de Vries <tom@codesourcery.com> * doc/sourcebuild.texi (Commands for use in dg-final, Scan optimization diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 40f0574..509f287 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -19872,7 +19872,7 @@ output_return_instruction (rtx operand, bool really_return, bool reverse, "msr%s\tAPSR_nzcvq, %%|lr", conditional); output_asm_insn (instr, & operand); - if (TARGET_HARD_FLOAT && !TARGET_THUMB1) + if (TARGET_HARD_FLOAT) { /* Clear the cumulative exception-status bits (0-4,7) and the condition code bits (28-31) of the FPSCR. We need to diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index ab63fc5..b01486a 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -125,7 +125,8 @@ extern tree arm_fp16_type_node; /* Use hardware floating point instructions. */ #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ && bitmap_bit_p (arm_active_target.isa, \ - isa_bit_vfpv2)) + isa_bit_vfpv2) \ + && TARGET_32BIT) #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT) /* User has permitted use of FP instructions, if they exist for this target. */ diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 31aff7d..a53180b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-12-19 Thomas Preud'homme <thomas.preudhomme@linaro.org> + + * gcc.target/arm/cmse/baseline/softfp.c: Force an FPU. + 2018-12-19 Tom de Vries <tdevries@suse.de> * gcc.dg/goacc/nvptx-merged-loop.c: Move to diff --git a/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c b/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c index 3d383ff..30b3eec 100644 --- a/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c +++ b/gcc/testsuite/gcc.target/arm/cmse/baseline/softfp.c @@ -1,5 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-mcmse -mfloat-abi=softfp" } */ +/* Force an FPU to test that it is ignored for Thumb-1 -like targets and that + no clearing of VFP register occurs. */ +/* { dg-options "-mcmse -mfloat-abi=softfp -mfpu=fpv5-d16" } */ double __attribute__ ((cmse_nonsecure_call)) (*bar) (float, double); |