Reorganize common mode; optimize SI*SI->DI on common/powerpc; Do not build power2/601 libraries

From-SVN: r10864

5 files changed, 303 insertions, 112 deletions

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 0435520..df6b789 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -323,6 +323,9 @@ rs6000_override_options (default_cpu)
 	}
     }
 
+  if (!WORDS_BIG_ENDIAN && !TARGET_POWER && !TARGET_POWERPC)
+    error ("-mcpu=common is not supported for little endian platforms");
+
 #ifdef SUBTARGET_OVERRIDE_OPTIONS
   SUBTARGET_OVERRIDE_OPTIONS;
 #endif
@@ -446,6 +449,77 @@ gpc_reg_operand (op, mode)
 	  && (GET_CODE (op) != REG || REGNO (op) >= 67 || REGNO (op) < 64));
 }
 
+/* Returns 1 if OP is register 0 or is a pseudo register.  */
+
+int
+gpc_reg0_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG || REGNO (op) == 0 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
+}
+
+/* Returns 1 if OP is register 3 or is a pseudo register.  */
+
+int
+gpc_reg3_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG || REGNO (op) == 3 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
+}
+
+/* Returns 1 if OP is register 4 or is a pseudo register.  */
+
+int
+gpc_reg4_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG || REGNO (op) == 4 || REGNO (op) >= FIRST_PSEUDO_REGISTER));
+}
+
+/* Returns 1 if OP is register 3 or 4 or is a pseudo register.  */
+
+int
+gpc_reg34_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG || REGNO (op) == 3 || REGNO (op) == 4
+	      || REGNO (op) >= FIRST_PSEUDO_REGISTER));
+}
+
+/* Returns 1 if OP is either a pseudo-register or CR1.  */
+
+int
+cc_reg1_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG
+	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
+	      || REGNO (op) == 69));
+}
+
+/* Returns 1 if OP is either a pseudo-register or CR0.  */
+
+int
+cc_reg0_operand (op, mode)
+     register rtx op;
+     enum machine_mode mode;
+{
+  return (register_operand (op, mode)
+	  && (GET_CODE (op) != REG
+	      || REGNO (op) >= FIRST_PSEUDO_REGISTER
+	      || REGNO (op) == 68));
+}
+
 /* Returns 1 if OP is either a pseudo-register or a register denoting a
    CR field.  */
 
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 97fca60..786c7e8 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -758,33 +758,89 @@ extern struct rs6000_cpu_select rs6000_select[];
    So make a class for registers valid as base registers.
 
    Also, cr0 is the only condition code register that can be used in
-   arithmetic insns, so make a separate class for it. */
+   arithmetic insns, so make a separate class for it.  Common mode
+   needs to clobber cr1, so add a class for that as well.  */
 
-enum reg_class { NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,
-  NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, CTR_REGS, LINK_OR_CTR_REGS,
-  SPECIAL_REGS, SPEC_OR_GEN_REGS, CR0_REGS, CR_REGS, NON_FLOAT_REGS,
-  ALL_REGS, LIM_REG_CLASSES };
+enum reg_class
+{
+  NO_REGS,
+  R0_REGS,
+  R3_REGS,
+  R4_REGS,
+  R34_REGS,
+  BASE_REGS,
+  GENERAL_REGS,
+  FLOAT_REGS,
+  NON_SPECIAL_REGS,
+  MQ_REGS,
+  LINK_REGS,
+  CTR_REGS,
+  LINK_OR_CTR_REGS,
+  SPECIAL_REGS,
+  SPEC_OR_GEN_REGS,
+  CR0_REGS,
+  CR1_REGS,
+  CR_REGS,
+  NON_FLOAT_REGS,
+  ALL_REGS,
+  LIM_REG_CLASSES
+};
 
 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 
 /* Give names of register classes as strings for dump file.   */
 
-#define REG_CLASS_NAMES					 	\
-  { "NO_REGS", "BASE_REGS", "GENERAL_REGS", "FLOAT_REGS",	\
-    "NON_SPECIAL_REGS", "MQ_REGS", "LINK_REGS", "CTR_REGS",	\
-    "LINK_OR_CTR_REGS", "SPECIAL_REGS", "SPEC_OR_GEN_REGS",	\
-    "CR0_REGS", "CR_REGS", "NON_FLOAT_REGS", "ALL_REGS" }
+#define REG_CLASS_NAMES							\
+{									\
+  "NO_REGS",								\
+  "R0_REGS",								\
+  "R3_REGS",								\
+  "R4_REGS",								\
+  "R34_REGS",								\
+  "BASE_REGS",								\
+  "GENERAL_REGS",							\
+  "FLOAT_REGS",								\
+  "NON_SPECIAL_REGS",							\
+  "MQ_REGS",								\
+  "LINK_REGS",								\
+  "CTR_REGS",								\
+  "LINK_OR_CTR_REGS",							\
+  "SPECIAL_REGS",							\
+  "SPEC_OR_GEN_REGS",							\
+  "CR0_REGS",								\
+  "CR1_REGS",								\
+  "CR_REGS",								\
+  "NON_FLOAT_REGS",							\
+  "ALL_REGS"								\
+}
 
 /* Define which registers fit in which classes.
    This is an initializer for a vector of HARD_REG_SET
    of length N_REG_CLASSES.  */
 
-#define REG_CLASS_CONTENTS				\
-  { {0, 0, 0}, {0xfffffffe, 0, 8}, {~0, 0, 8},		\
-    {0, ~0, 0}, {~0, ~0, 8}, {0, 0, 1}, {0, 0, 2},	\
-    {0, 0, 4}, {0, 0, 6}, {0, 0, 7}, {~0, 0, 15},	\
-    {0, 0, 16}, {0, 0, 0xff0}, {~0, 0, 0xffff},		\
-    {~0, ~0, 0xffff} }
+#define REG_CLASS_CONTENTS						\
+{									\
+  { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
+  { 0x00000001, 0x00000000, 0x00000000 },	/* R0_REGS */		\
+  { 0x00000008, 0x00000000, 0x00000000 },	/* R3_REGS */		\
+  { 0x00000010, 0x00000000, 0x00000000 },	/* R4_REGS */		\
+  { 0x00000018, 0x00000000, 0x00000000 },	/* R34_REGS */		\
+  { 0xfffffffe, 0x00000000, 0x00000008 },	/* BASE_REGS */		\
+  { 0xffffffff, 0x00000000, 0x00000008 },	/* GENERAL_REGS */	\
+  { 0x00000000, 0xffffffff, 0x00000000 },	/* FLOAT_REGS */	\
+  { 0xffffffff, 0xffffffff, 0x00000008 },	/* NON_SPECIAL_REGS */	\
+  { 0x00000000, 0x00000000, 0x00000001 },	/* MQ_REGS */		\
+  { 0x00000000, 0x00000000, 0x00000002 },	/* LINK_REGS */		\
+  { 0x00000000, 0x00000000, 0x00000004 },	/* CTR_REGS */		\
+  { 0x00000000, 0x00000000, 0x00000006 },	/* LINK_OR_CTR_REGS */	\
+  { 0x00000000, 0x00000000, 0x00000007 },	/* SPECIAL_REGS */	\
+  { 0xffffffff, 0x00000000, 0x0000000f },	/* SPEC_OR_GEN_REGS */	\
+  { 0x00000000, 0x00000000, 0x00000010 },	/* CR0_REGS */		\
+  { 0x00000000, 0x00000000, 0x00000020 },	/* CR1_REGS */		\
+  { 0x00000000, 0x00000000, 0x00000ff0 },	/* CR_REGS */		\
+  { 0xffffffff, 0x00000000, 0x0000ffff },	/* NON_FLOAT_REGS */	\
+  { 0xffffffff, 0xffffffff, 0x0000ffff }	/* ALL_REGS */		\
+}
 
 /* The same information, inverted:
    Return the class number of the smallest class containing
@@ -792,10 +848,13 @@ enum reg_class { NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,
    or could index an array.  */
 
 #define REGNO_REG_CLASS(REGNO)	\
- ((REGNO) == 0 ? GENERAL_REGS	\
+ ((REGNO) == 0 ? R0_REGS	\
+  : (REGNO) == 3 ? R3_REGS	\
+  : (REGNO) == 4 ? R4_REGS	\
   : (REGNO) < 32 ? BASE_REGS	\
   : FP_REGNO_P (REGNO) ? FLOAT_REGS \
   : (REGNO) == 68 ? CR0_REGS	\
+  : (REGNO) == 69 ? CR1_REGS	\
   : CR_REGNO_P (REGNO) ? CR_REGS \
   : (REGNO) == 64 ? MQ_REGS	\
   : (REGNO) == 65 ? LINK_REGS	\
@@ -816,8 +875,13 @@ enum reg_class { NO_REGS, BASE_REGS, GENERAL_REGS, FLOAT_REGS,
    : (C) == 'q' ? MQ_REGS	\
    : (C) == 'c' ? CTR_REGS	\
    : (C) == 'l' ? LINK_REGS	\
+   : (C) == 't' ? CR1_REGS	\
+   : (C) == 'u' ? R3_REGS	\
+   : (C) == 'v' ? R4_REGS	\
+   : (C) == 'w' ? R34_REGS	\
    : (C) == 'x' ? CR0_REGS	\
    : (C) == 'y' ? CR_REGS	\
+   : (C) == 'z' ? R0_REGS	\
    : NO_REGS)
 
 /* The letters I, J, K, L, M, N, and P in a register constraint string
@@ -2533,6 +2597,12 @@ do {									\
   {"u_short_cint_operand", {CONST_INT}},			\
   {"non_short_cint_operand", {CONST_INT}},			\
   {"gpc_reg_operand", {SUBREG, REG}},				\
+  {"gpc_reg0_operand", {SUBREG, REG}},				\
+  {"gpc_reg3_operand", {SUBREG, REG}},				\
+  {"gpc_reg4_operand", {SUBREG, REG}},				\
+  {"gpc_reg34_operand", {SUBREG, REG}},				\
+  {"cc_reg0_operand", {SUBREG, REG}},				\
+  {"cc_reg1_operand", {SUBREG, REG}},				\
   {"cc_reg_operand", {SUBREG, REG}},				\
   {"reg_or_short_operand", {SUBREG, REG, CONST_INT}},		\
   {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}},	\
@@ -2583,7 +2653,13 @@ extern int any_operand ();
 extern int short_cint_operand ();
 extern int u_short_cint_operand ();
 extern int non_short_cint_operand ();
+extern int gpc_reg0_operand ();
+extern int gpc_reg3_operand ();
+extern int gpc_reg4_operand ();
+extern int gpc_reg34_operand ();
 extern int gpc_reg_operand ();
+extern int cc_reg0_operand ();
+extern int cc_reg1_operand ();
 extern int cc_reg_operand ();
 extern int reg_or_short_operand ();
 extern int reg_or_neg_short_operand ();
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5ad55b1..dd8d4d4 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -1294,14 +1294,27 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_divss_call ());
+      emit_insn (gen_divmodsi4_common ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
       DONE;
     }
 }")
 
-(define_insn ""
+(define_insn "divmodsi4_common"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (set (reg:SI 4)
+	(mod:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (match_scratch:SI 1 "=z"))
+   (clobber (match_scratch:CC 2 "=x"))
+   (clobber (match_scratch:CC 3 "=t"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __divss"
+  [(set_attr "type" "jmpreg")])
+
+(define_insn "*divmodsi4_power"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "gpc_reg_operand" "r")))
@@ -1311,7 +1324,7 @@
   "divs %0,%1,%2"
   [(set_attr "type" "idiv")])
 
-(define_insn ""
+(define_insn "*divsi3_powerpc"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                 (match_operand:SI 2 "gpc_reg_operand" "r")))]
@@ -1330,13 +1343,24 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_quous_call ());
+      emit_insn (gen_udivsi3_common ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
 }")
 
-(define_insn ""
+(define_insn "udivsi3_common"
+  [(set (reg:SI 3)
+	(udiv:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (match_scratch:SI 1 "=z"))
+   (clobber (match_scratch:CC 2 "=x"))
+   (clobber (match_scratch:CC 3 "=t"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quous"
+  [(set_attr "type" "jmpreg")])
+
+(define_insn "*udivsi3_powerpc"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
         (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
                  (match_operand:SI 2 "gpc_reg_operand" "r")))]
@@ -1366,12 +1390,21 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_quoss_call ());
+      emit_insn (gen_divsi3_common ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
 }")
 
+(define_insn "divsi3_common"
+  [(set (reg:SI 3)
+	(div:SI (reg:SI 3) (reg:SI 4)))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (match_scratch:SI 1 "=z"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __quoss"
+  [(set_attr "type" "jmpreg")])
+
 (define_expand "modsi3"
   [(use (match_operand:SI 0 "gpc_reg_operand" ""))
    (use (match_operand:SI 1 "gpc_reg_operand" ""))
@@ -1499,7 +1532,7 @@
       {
 	emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
 	emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-	emit_insn (gen_divus_call ());
+	emit_insn (gen_udivmodsi4_common ());
 	emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
 	emit_move_insn (operands[3], gen_rtx (REG, SImode, 4));
 	DONE;
@@ -1525,64 +1558,19 @@
   DONE;
 }")
 
-;; AIX architecture-independent common-mode multiply (DImode),
-;; divide/modulus, and quotient subroutine calls.  Input operands in R3 and
-;; R4; results in R3 and sometimes R4; link register always clobbered by bla
-;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
-;; assumed unused if generating common-mode, so ignore.
-(define_insn "mulh_call"
-  [(set (reg:SI 3)
-	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
-			       (sign_extend:DI (reg:SI 4)))
-		      (const_int 32))))
-   (clobber (match_scratch:SI 0 "=l"))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mulh")
-
-(define_insn "mull_call"
-  [(set (reg:DI 3)
-	(mult:DI (sign_extend:DI (reg:SI 3))
-		 (sign_extend:DI (reg:SI 4))))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __mull")
-
-(define_insn "divss_call"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (set (reg:SI 4)
-	(mod:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divss")
-
-(define_insn "divus_call"
+(define_insn "udivmodsi4_common"
   [(set (reg:SI 3)
 	(udiv:SI (reg:SI 3) (reg:SI 4)))
    (set (reg:SI 4)
 	(umod:SI (reg:SI 3) (reg:SI 4)))
    (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __divus")
-
-(define_insn "quoss_call"
-  [(set (reg:SI 3)
-	(div:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))]
+   (clobber (match_scratch:SI 1 "=z"))
+   (clobber (match_scratch:CC 2 "=x"))
+   (clobber (match_scratch:CC 3 "=t"))]
   "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quoss")
+  "bla __divus"
+  [(set_attr "type" "jmpreg")])
 
-(define_insn "quous_call"
-  [(set (reg:SI 3)
-	(udiv:SI (reg:SI 3) (reg:SI 4)))
-   (clobber (match_scratch:SI 0 "=l"))
-   (clobber (reg:SI 0))]
-  "! TARGET_POWER && ! TARGET_POWERPC"
-  "bla __quous")
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
@@ -3684,14 +3672,7 @@
 {
   if (! TARGET_POWER && ! TARGET_POWERPC)
     {
-      int endian = (WORDS_BIG_ENDIAN == 0);
-      emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
-      emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_mull_call ());
-      emit_move_insn (operand_subword (operands[0], endian, 0, DImode),
-		      gen_rtx (REG, SImode, 3));
-      emit_move_insn (operand_subword (operands[0], 1 - endian, 0, DImode),
-		      gen_rtx (REG, SImode, 4));
+      emit_insn (gen_mulsidi3_common (operands[0], operands[1], operands[2]));
       DONE;
     }
   else if (TARGET_POWER)
@@ -3701,6 +3682,16 @@
     }
 }")
 
+(define_insn "mulsidi3_common"
+  [(set (match_operand:DI 0 "gpc_reg3_operand" "=w")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg3_operand" "%u"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg4_operand" "v"))))
+   (clobber (match_scratch:SI 3 "=l"))
+   (clobber (match_scratch:SI 4 "=z"))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mull"
+  [(set_attr "type" "jmpreg")])
+
 (define_insn "mulsidi3_mq"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
@@ -3711,7 +3702,7 @@
   [(set_attr "type" "imul")
    (set_attr "length" "8")])
 
-(define_insn ""
+(define_insn "*mulsidi3_powerpc"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
 	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
 		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
@@ -3725,6 +3716,26 @@
   [(set_attr "type" "imul")
    (set_attr "length" "8")])
 
+(define_split
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+  "TARGET_POWERPC && ! TARGET_POWERPC64"
+  [(set (match_dup 3)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
+			       (sign_extend:DI (match_dup 2)))
+		      (const_int 32))))
+   (set (match_dup 4)
+	(mult:SI (match_dup 1)
+		 (match_dup 2)))]
+  "
+{
+  int endian = (WORDS_BIG_ENDIAN == 0);
+  operands[3] = operand_subword (operands[0], endian, 0, DImode);
+  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
+}")
+
 (define_insn "umulsidi3"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
 	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
@@ -3739,6 +3750,26 @@
   [(set_attr "type" "imul")
    (set_attr "length" "8")])
 
+(define_split
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
+	(mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
+		 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
+  "TARGET_POWERPC && ! TARGET_POWERPC64"
+  [(set (match_dup 3)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
+			       (zero_extend:DI (match_dup 2)))
+		      (const_int 32))))
+   (set (match_dup 4)
+	(mult:SI (match_dup 1)
+		 (match_dup 2)))]
+  "
+{
+  int endian = (WORDS_BIG_ENDIAN == 0);
+  operands[3] = operand_subword (operands[0], endian, 0, DImode);
+  operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
+}")
+
 (define_expand "smulsi3_highpart"
   [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(truncate:SI
@@ -3754,7 +3785,7 @@
     {
       emit_move_insn (gen_rtx (REG, SImode, 3), operands[1]);
       emit_move_insn (gen_rtx (REG, SImode, 4), operands[2]);
-      emit_insn (gen_mulh_call ());
+      emit_insn (gen_smulsi3_highpart_common ());
       emit_move_insn (operands[0], gen_rtx (REG, SImode, 3));
       DONE;
     }
@@ -3765,26 +3796,34 @@
     }
 }")
 
+(define_insn "smulsi3_highpart_common"
+  [(set (reg:SI 3)
+	(truncate:SI
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
+			       (sign_extend:DI (reg:SI 4)))
+		      (const_int 32))))
+   (clobber (match_scratch:SI 0 "=l"))
+   (clobber (reg:SI 4))]
+  "! TARGET_POWER && ! TARGET_POWERPC"
+  "bla __mulh"
+  [(set_attr "type" "jmpreg")])
+
 (define_insn "smulsi3_highpart_mq"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))
    (clobber (match_scratch:SI 3 "=q"))]
   "TARGET_POWER"
   "mul %0,%1,%2"
   [(set_attr "type" "imul")])
 
-(define_insn ""
+(define_insn "*smulsi3_highpart_powerpc"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(truncate:SI
-	 (lshiftrt:DI (mult:DI (sign_extend:DI
-				(match_operand:SI 1 "gpc_reg_operand" "%r"))
-			       (sign_extend:DI
-				(match_operand:SI 2 "gpc_reg_operand" "r")))
+	 (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
+			       (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		      (const_int 32))))]
   "TARGET_POWERPC"
   "mulhw %0,%1,%2"
diff --git a/gcc/config/rs6000/t-newas b/gcc/config/rs6000/t-newas
index 9778b2b..823b03b 100644
--- a/gcc/config/rs6000/t-newas
+++ b/gcc/config/rs6000/t-newas
@@ -17,18 +17,21 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
 # different processor models
 
 MULTILIB_OPTIONS	= msoft-float \
-			  mcpu=common/mcpu=power/mcpu=powerpc/mcpu=601/mcpu=power2
+			  mcpu=common/mcpu=power/mcpu=powerpc
 
 MULTILIB_DIRNAMES	= soft-float \
-			  common power powerpc 601 power2
+			  common power powerpc
 
 MULTILIB_MATCHES	= msoft-float=mcpu?403 \
 			  mcpu?power=mpower \
 			  mcpu?power=mrios1 \
-			  mcpu?power=mcpu=rios1 \
-			  mcpu?power2=mpower2 \
-			  mcpu?power2=mrios2 \
-			  mcpu?power2=mcpu=rios2 \
+			  mcpu?power=mcpu?rios1 \
+			  mcpu?power=mcpu?rsc \
+			  mcpu?power=mcpu?rsc1 \
+			  mcpu?power=mpower2 \
+			  mcpu?power=mrios2 \
+			  mcpu?power=mcpu=rios2 \
+			  mcpu?powerpc=mcpu?601 \
 			  mcpu?powerpc=mcpu?602 \
 			  mcpu?powerpc=mcpu?603 \
 			  mcpu?powerpc=mcpu?603e \
@@ -37,9 +40,7 @@ MULTILIB_MATCHES	= msoft-float=mcpu?403 \
 			  mcpu?powerpc=mcpu?403 \
 			  mcpu?powerpc=mpowerpc \
 			  mcpu?powerpc=mpowerpc-gpopt \
-			  mcpu?powerpc=mpowerpc-gfxopt \
-			  mcpu?601=mcpu?rsc \
-			  mcpu?601=mcpu?rsc1
+			  mcpu?powerpc=mpowerpc-gfxopt
 
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
diff --git a/gcc/config/rs6000/t-xnewas b/gcc/config/rs6000/t-xnewas
index ba97287..285f825 100644
--- a/gcc/config/rs6000/t-xnewas
+++ b/gcc/config/rs6000/t-xnewas
@@ -23,18 +23,21 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
 # different processor models
 
 MULTILIB_OPTIONS	= msoft-float \
-			  mcpu=common/mcpu=power/mcpu=powerpc/mcpu=601/mcpu=power2
+			  mcpu=common/mcpu=power/mcpu=powerpc
 
 MULTILIB_DIRNAMES	= soft-float \
-			  common power powerpc 601 power2
+			  common power powerpc
 
 MULTILIB_MATCHES	= msoft-float=mcpu?403 \
 			  mcpu?power=mpower \
 			  mcpu?power=mrios1 \
-			  mcpu?power=mcpu=rios1 \
-			  mcpu?power2=mpower2 \
-			  mcpu?power2=mrios2 \
-			  mcpu?power2=mcpu=rios2 \
+			  mcpu?power=mcpu?rios1 \
+			  mcpu?power=mcpu?rsc \
+			  mcpu?power=mcpu?rsc1 \
+			  mcpu?power=mpower2 \
+			  mcpu?power=mrios2 \
+			  mcpu?power=mcpu=rios2 \
+			  mcpu?powerpc=mcpu?601 \
 			  mcpu?powerpc=mcpu?602 \
 			  mcpu?powerpc=mcpu?603 \
 			  mcpu?powerpc=mcpu?603e \
@@ -43,9 +46,7 @@ MULTILIB_MATCHES	= msoft-float=mcpu?403 \
 			  mcpu?powerpc=mcpu?403 \
 			  mcpu?powerpc=mpowerpc \
 			  mcpu?powerpc=mpowerpc-gpopt \
-			  mcpu?powerpc=mpowerpc-gfxopt \
-			  mcpu?601=mcpu?rsc \
-			  mcpu?601=mcpu?rsc1
+			  mcpu?powerpc=mpowerpc-gfxopt
 
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib