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| author | Roger Sayle <roger@eyesopen.com> | 2005-01-31 06:04:07 +0000 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2005-01-31 06:04:07 +0000 |
| commit | ebcaaa2152486039f548259cc008ba5b3243d393 (patch) | |
| tree | 4090cccce5fd6a27421275731e160d27d4ff7136 | |
| parent | 6cc37e7e24bb91d009d0a0c9ae9f37dd3c329d74 (diff) | |
| download | gcc-ebcaaa2152486039f548259cc008ba5b3243d393.zip gcc-ebcaaa2152486039f548259cc008ba5b3243d393.tar.gz gcc-ebcaaa2152486039f548259cc008ba5b3243d393.tar.bz2 | |
re PR middle-end/19697 (gcc.c-torture/execute/ieee/mzero6.c:24: error: unrecognizable insn)
PR middle-end/19697
* config/pa/pa.md (anddi3, iordi3): On HPPA64, disallow an integer
constant as the second operand and a register as the third.
From-SVN: r94468
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/pa/pa.md | 38 |
2 files changed, 14 insertions, 30 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e66f1f8..79a2feb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2005-01-30 Roger Sayle <roger@eyesopen.com> + + PR middle-end/19697 + * config/pa/pa.md (anddi3, iordi3): On HPPA64, disallow an integer + constant as the second operand and a register as the third. + 2005-01-31 Danny Smith <dannysmith@users.sourceforge.net> PR target/19704 diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index cb88288..9a434a6 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -5441,25 +5441,14 @@ (define_expand "anddi3" [(set (match_operand:DI 0 "register_operand" "") - (and:DI (match_operand:DI 1 "and_operand" "") + (and:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "and_operand" "")))] "" " { - if (TARGET_64BIT) - { - /* One operand must be a register operand. */ - if (!register_operand (operands[1], DImode) - && !register_operand (operands[2], DImode)) - FAIL; - } - else - { - /* Both operands must be register operands. */ - if (!register_operand (operands[1], DImode) - || !register_operand (operands[2], DImode)) - FAIL; - } + /* Both operands must be register operands. */ + if (!TARGET_64BIT && !register_operand (operands[2], DImode)) + FAIL; }") (define_insn "" @@ -5520,25 +5509,14 @@ (define_expand "iordi3" [(set (match_operand:DI 0 "register_operand" "") - (ior:DI (match_operand:DI 1 "ior_operand" "") + (ior:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "ior_operand" "")))] "" " { - if (TARGET_64BIT) - { - /* One operand must be a register operand. */ - if (!register_operand (operands[1], DImode) - && !register_operand (operands[2], DImode)) - FAIL; - } - else - { - /* Both operands must be register operands. */ - if (!register_operand (operands[1], DImode) - || !register_operand (operands[2], DImode)) - FAIL; - } + /* Both operands must be register operands. */ + if (!TARGET_64BIT && !register_operand (operands[2], DImode)) + FAIL; }") (define_insn "" |