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| author | Xionghu Luo <xionghuluo@tencent.com> | 2022-10-12 10:43:38 +0800 |
|---|---|---|
| committer | Haochen Gui <guihaoc@gcc.gnu.org> | 2022-11-02 16:40:44 +0800 |
| commit | eaba55ffef961c28f6a15d845a4d6b77b8a8bab1 (patch) | |
| tree | 8aac6befbe4ce31f82fb631f1abeae2e56b736c7 | |
| parent | 74e904bdcac3abdd0453daf3b6195d17e44b4cee (diff) | |
| download | gcc-eaba55ffef961c28f6a15d845a4d6b77b8a8bab1.zip gcc-eaba55ffef961c28f6a15d845a4d6b77b8a8bab1.tar.gz gcc-eaba55ffef961c28f6a15d845a4d6b77b8a8bab1.tar.bz2 | |
rs6000: Byte reverse V8HI on Power8 by vector rotation.
gcc/
PR target/100866
* config/rs6000/altivec.md: (*altivec_vrl<VI_char>): Named to...
(altivec_vrl<VI_char>): ...this.
* config/rs6000/vsx.md (revb_<mode>): Call vspltish and vrlh when
target is Power8 and mode is V8HI.
gcc/testsuite/
PR target/100866
* gcc.target/powerpc/pr100866-2.c: New.
| -rw-r--r-- | gcc/config/rs6000/altivec.md | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 21 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/powerpc/pr100866-2.c | 13 |
3 files changed, 29 insertions, 7 deletions
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index 2c4940f..8466007 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -1875,7 +1875,7 @@ } [(set_attr "type" "vecperm")]) -(define_insn "*altivec_vrl<VI_char>" +(define_insn "altivec_vrl<VI_char>" [(set (match_operand:VI2 0 "register_operand" "=v") (rotate:VI2 (match_operand:VI2 1 "register_operand" "v") (match_operand:VI2 2 "register_operand" "v")))] diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e0e34a7..fb5cf04 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6087,12 +6087,21 @@ emit_insn (gen_p9_xxbr<VSX_XXBR>_<mode> (operands[0], operands[1])); else { - /* Want to have the elements in reverse order relative - to the endian mode in use, i.e. in LE mode, put elements - in BE order. */ - rtx sel = swap_endian_selector_for_mode(<MODE>mode); - emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], - operands[1], sel)); + if (<MODE>mode == V8HImode) + { + rtx splt = gen_reg_rtx (V8HImode); + emit_insn (gen_altivec_vspltish (splt, GEN_INT (8))); + emit_insn (gen_altivec_vrlh (operands[0], operands[1], splt)); + } + else + { + /* Want to have the elements in reverse order relative + to the endian mode in use, i.e. in LE mode, put elements + in BE order. */ + rtx sel = swap_endian_selector_for_mode (<MODE>mode); + emit_insn (gen_altivec_vperm_<mode> (operands[0], operands[1], + operands[1], sel)); + } } DONE; diff --git a/gcc/testsuite/gcc.target/powerpc/pr100866-2.c b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c new file mode 100644 index 0000000..4357d1b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/pr100866-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-O2 -mdejagnu-cpu=power8" } */ +/* { dg-final { scan-assembler {\mvspltish\M} } } */ +/* { dg-final { scan-assembler {\mvrlh\M} } } */ + +#include <altivec.h> + +vector unsigned short revb(vector unsigned short a) +{ + return vec_revb(a); +} + |