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| author | Jeff Law <jlaw@ventanamicro.com> | 2024-01-14 07:53:49 -0700 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-01-14 07:53:49 -0700 |
| commit | e927cfa842c16bea902500e69ab4eca2ef15af4e (patch) | |
| tree | 226ebae3276bf32fe37846d8fd13e04bcb9190f6 | |
| parent | ed5bf2080c538b63459891dbd8f217823f7c6127 (diff) | |
| download | gcc-e927cfa842c16bea902500e69ab4eca2ef15af4e.zip gcc-e927cfa842c16bea902500e69ab4eca2ef15af4e.tar.gz gcc-e927cfa842c16bea902500e69ab4eca2ef15af4e.tar.bz2 | |
[committed] Fix MIPS bootstrap
mips bootstraps have been broken for a while. They've been triggering an error
about mutually exclusive equal-tests always being false when building
gencondmd.
This was ultimately tracked down to the ior<mode>3_mips16_asmacro pattern. The
pattern uses the GPR mode iterator which looks like this:
(define_mode_iterator GPR [SI (DI "TARGET_64BIT")])
The condition for the pattern looks like this:
"ISA_HAS_MIPS16E2"
And if you dig into ISA_HAS_MIPS16E2:
/* The MIPS16e V2 instructions are available. */
&& !TARGET_64BIT)
The way the mode iterator is handled is by adding its condition to the
pattern's condition when we expand copies of the pattern resulting in this
condition for one of the two generated patterns:
(TARGET_MIPS16 && TARGET_MIPS16E2 && !TARGET_64BIT) && TARGET_64BIT
This can never be true because of the TARGET_64BIT tests.
The fix is trivial. Don't use a mode iterator on that pattern.
Bootstrapped on mips64el. I don't have any tests to compare against, so no
regression test data.
gcc/
* config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
not the GPR iterator. Adjust pattern name and mode attribute
accordingly.
| -rw-r--r-- | gcc/config/mips/mips.md | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 17dfcbd..b0fb585 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3440,16 +3440,16 @@ (set_attr "compression" "micromips,*,*") (set_attr "mode" "<MODE>")]) -(define_insn "*ior<mode>3_mips16_asmacro" - [(set (match_operand:GPR 0 "register_operand" "=d,d") - (ior:GPR (match_operand:GPR 1 "register_operand" "%0,0") - (match_operand:GPR 2 "uns_arith_operand" "d,K")))] +(define_insn "*iorsi3_mips16_asmacro" + [(set (match_operand:SI 0 "register_operand" "=d,d") + (ior:SI (match_operand:SI 1 "register_operand" "%0,0") + (match_operand:SI 2 "uns_arith_operand" "d,K")))] "ISA_HAS_MIPS16E2" "@ or\t%0,%2 ori\t%0,%x2" [(set_attr "alu_type" "or") - (set_attr "mode" "<MODE>") + (set_attr "mode" "SI") (set_attr "extended_mips16" "*,yes")]) (define_insn "*ior<mode>3_mips16" |