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| author | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-20 16:43:17 +0000 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@gcc.gnu.org> | 2017-03-20 16:43:17 +0000 |
| commit | e05a9f8e560a09d920555dec2960497dcb9e9ede (patch) | |
| tree | 385a82b5b6098b1d4c2307ccaf95431cb066bbc2 | |
| parent | 3611534e1f90fc05f363cc7b40d45fcd295c26ad (diff) | |
| download | gcc-e05a9f8e560a09d920555dec2960497dcb9e9ede.zip gcc-e05a9f8e560a09d920555dec2960497dcb9e9ede.tar.gz gcc-e05a9f8e560a09d920555dec2960497dcb9e9ede.tar.bz2 | |
Use more conservative fences on RISC-V
The RISC-V memory model is still in the process of being formally
specified, so for now we're going to be safe and add the I/O bits to
userspace fences because there's no way to know if userspace is touching
memory-mapped I/O regions at compile time.
This will have no impact on existing microarchitecutres because they
treat all fences conservatively.
gcc/ChangeLog:
2017-03-17 Palmer Dabbelt <palmer@dabbelt.com>
* config/riscv/riscv.c (riscv_print_operand): Use "fence
iorw,ow".
* config/riscv/sync.mc (mem_thread_fence_1): Use "fence
iorw,iorw".
From-SVN: r246282
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.c | 2 | ||||
| -rw-r--r-- | gcc/config/riscv/sync.md | 2 |
3 files changed, 9 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 90c8556..487a09b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2017-03-17 Palmer Dabbelt <palmer@dabbelt.com> + + * config/riscv/riscv.c (riscv_print_operand): Use "fence + iorw,ow". + * config/riscv/sync.mc (mem_thread_fence_1): Use "fence + iorw,iorw". + 2017-03-20 Marek Polacek <polacek@redhat.com> PR sanitizer/80063 diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 25cc803..fa93c3c 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -2794,7 +2794,7 @@ riscv_print_operand (FILE *file, rtx op, int letter) case 'F': if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) - fputs ("fence rw,w; ", file); + fputs ("fence iorw,ow; ", file); break; default: diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md index 09970b9..cde19e3 100644 --- a/gcc/config/riscv/sync.md +++ b/gcc/config/riscv/sync.md @@ -53,7 +53,7 @@ (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER)) (match_operand:SI 1 "const_int_operand" "")] ;; model "" - "fence\trw,rw") + "fence\tiorw,iorw") ;; Atomic memory operations. |