arm: [MVE intrinsics] factorize vmaxaq vminaq

Factorize vmaxaq vminaq so that they use the same pattern.

2022-09-08  Christophe Lyon  <christophe.lyon@arm.com>

	gcc/
	* config/arm/iterators.md (MVE_VMAXAVMINAQ, MVE_VMAXAVMINAQ_M):
	New.
	(mve_insn): Add vmaxa, vmina.
	(supf): Add VMAXAQ_S, VMAXAQ_M_S, VMINAQ_S, VMINAQ_M_S.
	* config/arm/mve.md (mve_vmaxaq_s<mode>, mve_vminaq_s<mode>):
	Merge into ...
	(@mve_<mve_insn>q_<supf><mode>): ... this.
	(mve_vmaxaq_m_s<mode>, mve_vminaq_m_s<mode>): Merge into ...
	(@mve_<mve_insn>q_m_<supf><mode>): ... this.

2 files changed, 28 insertions, 39 deletions

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 8edbf5a..3c70fd7 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -621,6 +621,16 @@
 		     VMINNMAQ_M_F
 		     ])
 
+(define_int_iterator MVE_VMAXAVMINAQ [
+		     VMAXAQ_S
+		     VMINAQ_S
+		     ])
+
+(define_int_iterator MVE_VMAXAVMINAQ_M [
+		     VMAXAQ_M_S
+		     VMINAQ_M_S
+		     ])
+
 (define_int_iterator MVE_MOVN [
 		     VMOVNBQ_S VMOVNBQ_U
 		     VMOVNTQ_S VMOVNTQ_U
@@ -670,6 +680,8 @@
 		 (VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
 		 (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
 		 (VHSUBQ_S "vhsub") (VHSUBQ_U "vhsub")
+		 (VMAXAQ_M_S "vmaxa")
+		 (VMAXAQ_S "vmaxa")
 		 (VMAXAVQ_P_S "vmaxav")
 		 (VMAXAVQ_S "vmaxav")
 		 (VMAXNMAQ_F "vmaxnma")
@@ -682,6 +694,8 @@
 		 (VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
 		 (VMAXVQ_P_S "vmaxv") (VMAXVQ_P_U "vmaxv")
 		 (VMAXVQ_S "vmaxv") (VMAXVQ_U "vmaxv")
+		 (VMINAQ_M_S "vmina")
+		 (VMINAQ_S "vmina")
 		 (VMINAVQ_P_S "vminav")
 		 (VMINAVQ_S "vminav")
 		 (VMINNMAQ_F "vminnma")
@@ -2064,6 +2078,10 @@
 		       (VMAXAVQ_P_S "s")
 		       (VMINAVQ_S "s")
 		       (VMINAVQ_P_S "s")
+		       (VMAXAQ_S "s")
+		       (VMAXAQ_M_S "s")
+		       (VMINAQ_S "s")
+		       (VMINAQ_M_S "s")
 		       ])
 
 ;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index ef0b6fd..45bca6d 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -948,17 +948,18 @@
 ])
 
 ;;
-;; [vmaxaq_s])
+;; [vmaxaq_s]
+;; [vminaq_s]
 ;;
-(define_insn "mve_vmaxaq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMAXAQ_S))
+	 MVE_VMAXAVMINAQ))
   ]
   "TARGET_HAVE_MVE"
-  "vmaxa.s%#<V_sz_elem>	%q0, %q2"
+  "<mve_insn>.s%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
 ])
 
@@ -997,21 +998,6 @@
 ])
 
 ;;
-;; [vminaq_s])
-;;
-(define_insn "mve_vminaq_s<mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")]
-	 VMINAQ_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vmina.s%#<V_sz_elem>\t%q0, %q2"
-  [(set_attr "type" "mve_move")
-])
-
-;;
 ;; [vmladavq_u, vmladavq_s])
 ;;
 (define_insn "mve_vmladavq_<supf><mode>"
@@ -2239,18 +2225,19 @@
    (set_attr "length""8")])
 
 ;;
-;; [vmaxaq_m_s])
+;; [vmaxaq_m_s]
+;; [vminaq_m_s]
 ;;
-(define_insn "mve_vmaxaq_m_s<mode>"
+(define_insn "@mve_<mve_insn>q_m_<supf><mode>"
   [
    (set (match_operand:MVE_2 0 "s_register_operand" "=w")
 	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
 		       (match_operand:MVE_2 2 "s_register_operand" "w")
 		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMAXAQ_M_S))
+	 MVE_VMAXAVMINAQ_M))
   ]
   "TARGET_HAVE_MVE"
-  "vpst\;vmaxat.s%#<V_sz_elem>	%q0, %q2"
+  "vpst\;<mve_insn>t.s%#<V_sz_elem>\t%q0, %q2"
   [(set_attr "type" "mve_move")
    (set_attr "length""8")])
 
@@ -2274,22 +2261,6 @@
    (set_attr "length""8")])
 
 ;;
-;; [vminaq_m_s])
-;;
-(define_insn "mve_vminaq_m_s<mode>"
-  [
-   (set (match_operand:MVE_2 0 "s_register_operand" "=w")
-	(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "0")
-		       (match_operand:MVE_2 2 "s_register_operand" "w")
-		       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
-	 VMINAQ_M_S))
-  ]
-  "TARGET_HAVE_MVE"
-  "vpst\;vminat.s%#<V_sz_elem>	%q0, %q2"
-  [(set_attr "type" "mve_move")
-   (set_attr "length""8")])
-
-;;
 ;; [vmladavaq_u, vmladavaq_s])
 ;;
 (define_insn "mve_vmladavaq_<supf><mode>"