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author | Segher Boessenkool <segher@kernel.crashing.org> | 2018-12-19 14:54:08 +0100 |
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committer | Segher Boessenkool <segher@gcc.gnu.org> | 2018-12-19 14:54:08 +0100 |
commit | dc355223e465d3a2c090f34afd2ce965d20de199 (patch) | |
tree | 535b9b083f647b41d10de513d1e2873d40b9d982 | |
parent | 08926e6f5bbf23d1eebc776d84d648f8b5836931 (diff) | |
download | gcc-dc355223e465d3a2c090f34afd2ce965d20de199.zip gcc-dc355223e465d3a2c090f34afd2ce965d20de199.tar.gz gcc-dc355223e465d3a2c090f34afd2ce965d20de199.tar.bz2 |
Restrict a VSX extract to TARGET_POWERPC64 (PR88213)
This pattern optimises a scalar extract from a vector loaded from
memory to be just a scalar load from memory. But to do a 64-bit
integer load you need 64-bit integer registers, which needs
TARGET_POWERPC64.
PR target/88213
* config/rs6000/vsx.md (*vsx_extract_<P:mode>_<VSX_D:mode>_load):
Require TARGET_POWERPC64.
From-SVN: r267263
-rw-r--r-- | gcc/ChangeLog | 6 | ||||
-rw-r--r-- | gcc/config/rs6000/vsx.md | 2 |
2 files changed, 7 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 56e50e2..6fe6ec3 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-12-19 Segher Boessenkool <segher@kernel.crashing.org> + + PR target/88213 + * config/rs6000/vsx.md (*vsx_extract_<P:mode>_<VSX_D:mode>_load): + Require TARGET_POWERPC64. + 2018-12-19 Richard Biener <rguenther@suse.de> PR tree-optimization/88533 diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 65a9892..38223a5 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3257,7 +3257,7 @@ (match_operand:VSX_D 1 "memory_operand" "m,m") (parallel [(match_operand:QI 2 "const_0_to_1_operand" "n,n")]))) (clobber (match_scratch:P 3 "=&b,&b"))] - "VECTOR_MEM_VSX_P (<VSX_D:MODE>mode)" + "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<VSX_D:MODE>mode)" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] |