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| author | liuhongt <hongtao.liu@intel.com> | 2023-09-05 13:07:04 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2023-09-08 07:02:11 +0800 |
| commit | daaed758517c81fc8f8bc6502be648aca51ab278 (patch) | |
| tree | 930f79bf38abacff68f3c926721f9a4bbf066e4f | |
| parent | 1b761fede44afac5fa72e77caced9beda93fb381 (diff) | |
| download | gcc-daaed758517c81fc8f8bc6502be648aca51ab278.zip gcc-daaed758517c81fc8f8bc6502be648aca51ab278.tar.gz gcc-daaed758517c81fc8f8bc6502be648aca51ab278.tar.bz2 | |
Support vpermw/vpermi2w/vpermt2w instructions for vector HF/BFmodes.
gcc/ChangeLog:
* config/i386/sse.md
(<avx512>_vpermt2var<mode>3<sd_maskz_name>): New define_insn.
(VHFBF_AVX512VL): New mode iterator.
(VI2HFBF_AVX512VL): New mode iterator.
| -rw-r--r-- | gcc/config/i386/sse.md | 32 |
1 files changed, 28 insertions, 4 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 6d3ae8d..12fe979 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -466,6 +466,10 @@ (define_mode_iterator VHF_AVX512VL [V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL")]) +(define_mode_iterator VHFBF_AVX512VL + [V32HF (V16HF "TARGET_AVX512VL") (V8HF "TARGET_AVX512VL") + V32BF (V16BF "TARGET_AVX512VL") (V8BF "TARGET_AVX512VL")]) + ;; All vector integer modes (define_mode_iterator VI [(V16SI "TARGET_AVX512F") (V8DI "TARGET_AVX512F") @@ -565,6 +569,11 @@ (define_mode_iterator VI2_AVX512VL [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI]) +(define_mode_iterator VI2HFBF_AVX512VL + [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI + (V8HF "TARGET_AVX512VL") (V16HF "TARGET_AVX512VL") V32HF + (V8BF "TARGET_AVX512VL") (V16BF "TARGET_AVX512VL") V32BF]) + (define_mode_iterator VI2H_AVX512VL [(V8HI "TARGET_AVX512VL") (V16HI "TARGET_AVX512VL") V32HI (V8SI "TARGET_AVX512VL") V16SI @@ -26110,13 +26119,13 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "<avx512>_permvar<mode><mask_name>" - [(set (match_operand:VI2_AVX512VL 0 "register_operand" "=v") - (unspec:VI2_AVX512VL - [(match_operand:VI2_AVX512VL 1 "nonimmediate_operand" "vm") + [(set (match_operand:VI2HFBF_AVX512VL 0 "register_operand" "=v") + (unspec:VI2HFBF_AVX512VL + [(match_operand:VI2HFBF_AVX512VL 1 "nonimmediate_operand" "vm") (match_operand:<sseintvecmode> 2 "register_operand" "v")] UNSPEC_VPERMVAR))] "TARGET_AVX512BW && <mask_mode512bit_condition>" - "vperm<ssemodesuffix>\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}" + "vpermw\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}" [(set_attr "type" "sselog") (set_attr "prefix" "<mask_prefix2>") (set_attr "mode" "<sseinsnmode>")]) @@ -26987,6 +26996,21 @@ (set_attr "prefix" "evex") (set_attr "mode" "<sseinsnmode>")]) +(define_insn "<avx512>_vpermt2var<mode>3<sd_maskz_name>" + [(set (match_operand:VHFBF_AVX512VL 0 "register_operand" "=v,v") + (unspec:VHFBF_AVX512VL + [(match_operand:<sseintvecmode> 1 "register_operand" "v,0") + (match_operand:VHFBF_AVX512VL 2 "register_operand" "0,v") + (match_operand:VHFBF_AVX512VL 3 "nonimmediate_operand" "vm,vm")] + UNSPEC_VPERMT2))] + "TARGET_AVX512BW" + "@ + vpermt2w\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3} + vpermi2w\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "<sseinsnmode>")]) + (define_insn "<avx512>_vpermt2var<mode>3_mask" [(set (match_operand:VPERMI2 0 "register_operand" "=v") (vec_merge:VPERMI2 |