diff options
| author | H.J. Lu <hongjiu.lu@intel.com> | 2010-11-05 12:53:39 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2010-11-05 05:53:39 -0700 |
| commit | d73ee4e74eb82f29e5949c13c6544b50d0f96d4c (patch) | |
| tree | 699be373e4c6e336a681bdbc2e0329aab8120291 | |
| parent | 8b7e852901472ee45e1b1e3c2dbfa410eb892290 (diff) | |
| download | gcc-d73ee4e74eb82f29e5949c13c6544b50d0f96d4c.zip gcc-d73ee4e74eb82f29e5949c13c6544b50d0f96d4c.tar.gz gcc-d73ee4e74eb82f29e5949c13c6544b50d0f96d4c.tar.bz2 | |
Check 256bit AVX register in move expanders.
gcc/
2010-11-05 H.J. Lu <hongjiu.lu@intel.com>
Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (ix86_expand_move): Set use_avx256_p if
256bit AVX register is used.
(ix86_expand_vector_move_misalign): Likewise.
(ix86_expand_vector_move): Replace use_avx256_p with
VALID_AVX256_REG_MODE.
gcc/testsuite/
2010-11-05 H.J. Lu <hongjiu.lu@intel.com>
* gcc.target/i386/avx-vzeroupper-19.c: New.
Co-Authored-By: Uros Bizjak <ubizjak@gmail.com>
From-SVN: r166358
| -rw-r--r-- | gcc/ChangeLog | 9 | ||||
| -rw-r--r-- | gcc/config/i386/i386.c | 8 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c | 17 |
4 files changed, 37 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index b1c9f5c..1d0902f 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2010-11-05 H.J. Lu <hongjiu.lu@intel.com> + Uros Bizjak <ubizjak@gmail.com> + + * config/i386/i386.c (ix86_expand_move): Set use_avx256_p if + 256bit AVX register is used. + (ix86_expand_vector_move_misalign): Likewise. + (ix86_expand_vector_move): Replace use_avx256_p with + VALID_AVX256_REG_MODE. + 2010-11-05 Joern Rennecke <amylaar@spamcop.net> PR target/44750 diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3558899..00febba 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -15000,6 +15000,9 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) rtx op0, op1; enum tls_model model; + if (VALID_AVX256_REG_MODE (mode)) + cfun->machine->use_avx256_p = true; + op0 = operands[0]; op1 = operands[1]; @@ -15144,7 +15147,7 @@ ix86_expand_vector_move (enum machine_mode mode, rtx operands[]) rtx op0 = operands[0], op1 = operands[1]; unsigned int align = GET_MODE_ALIGNMENT (mode); - if (use_avx256_p (mode, NULL_TREE)) + if (VALID_AVX256_REG_MODE (mode)) cfun->machine->use_avx256_p = true; /* Force constants other than zero into memory. We do not know how @@ -15253,6 +15256,9 @@ ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) { rtx op0, op1, m; + if (VALID_AVX256_REG_MODE (mode)) + cfun->machine->use_avx256_p = true; + op0 = operands[0]; op1 = operands[1]; diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 9631772..c7189a9 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2010-11-05 H.J. Lu <hongjiu.lu@intel.com> + + * gcc.target/i386/avx-vzeroupper-19.c: New. + 2010-11-05 Jakub Jelinek <jakub@redhat.com> PR tree-optimization/46099 diff --git a/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c new file mode 100644 index 0000000..602de87 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx-vzeroupper-19.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -mavx -mtune=generic -dp" } */ + +void feat_s3_cep_dcep (int cepsize_used, float **mfc, float **feat) +{ + float *f; + float *w, *_w; + int i; + __builtin_memcpy (feat[0], mfc[0], cepsize_used * sizeof(float)); + f = feat[0] + cepsize_used; + w = mfc[2]; + _w = mfc[-2]; + for (i = 0; i < cepsize_used; i++) + f[i] = w[i] - _w[i]; +} + +/* { dg-final { scan-assembler-times "avx_vzeroupper" 1 } } */ |