re PR target/84226 (ICE in simplify_const_unary_operation, at simplify-rtx.c:1974 on ppc64le)

	PR target/84226
	* config/rs6000/vsx.md (p9_xxbrq_v16qi): Change input operand
	constraint from =wa to wa.  Avoid a subreg on the output operand,
	instead use a pseudo and subreg it in a move.
	(p9_xxbrd_<mode>): Changed to ...
	(p9_xxbrd_v2di): ... this insn, without VSX_D iterator.
	(p9_xxbrd_v2df): New expander.
	(p9_xxbrw_<mode>): Changed to ...
	(p9_xxbrw_v4si): ... this insn, without VSX_W iterator.
	(p9_xxbrw_v4sf): New expander.

	* gcc.target/powerpc/pr84226.c: New test.

From-SVN: r257536

4 files changed, 61 insertions, 12 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 7f19858..4ac7fff 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,7 +1,20 @@
+2018-02-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/84226
+	* config/rs6000/vsx.md (p9_xxbrq_v16qi): Change input operand
+	constraint from =wa to wa.  Avoid a subreg on the output operand,
+	instead use a pseudo and subreg it in a move.
+	(p9_xxbrd_<mode>): Changed to ...
+	(p9_xxbrd_v2di): ... this insn, without VSX_D iterator.
+	(p9_xxbrd_v2df): New expander.
+	(p9_xxbrw_<mode>): Changed to ...
+	(p9_xxbrw_v4si): ... this insn, without VSX_W iterator.
+	(p9_xxbrw_v4sf): New expander.
+
 2018-02-09  Sebastian Perta  <sebastian.perta@renesas.com>
 
-	*config/rx.md: updated "movsicc" expand to be matched by GCC
-	*testsuite/gcc.target/rx/movsicc.c: new test case
+	* config/rx.md: updated "movsicc" expand to be matched by GCC
+	* testsuite/gcc.target/rx/movsicc.c: new test case
 
 2018-02-09  Peter Bergner  <bergner@vnet.ibm.com>
 
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 86efdce..6f0bd09 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5363,35 +5363,60 @@
 
 (define_expand "p9_xxbrq_v16qi"
   [(use (match_operand:V16QI 0 "vsx_register_operand" "=wa"))
-   (use (match_operand:V16QI 1 "vsx_register_operand" "=wa"))]
+   (use (match_operand:V16QI 1 "vsx_register_operand" "wa"))]
   "TARGET_P9_VECTOR"
 {
-  rtx op0 = gen_lowpart (V1TImode, operands[0]);
+  rtx op0 = gen_reg_rtx (V1TImode);
   rtx op1 = gen_lowpart (V1TImode, operands[1]);
   emit_insn (gen_p9_xxbrq_v1ti (op0, op1));
+  emit_move_insn (operands[0], gen_lowpart (V16QImode, op0));
   DONE;
 })
 
 ;; Swap all bytes in each 64-bit element
-(define_insn "p9_xxbrd_<mode>"
-  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wa")
-	(bswap:VSX_D (match_operand:VSX_D 1 "vsx_register_operand" "wa")))]
+(define_insn "p9_xxbrd_v2di"
+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
+	(bswap:V2DI (match_operand:V2DI 1 "vsx_register_operand" "wa")))]
   "TARGET_P9_VECTOR"
   "xxbrd %x0,%x1"
   [(set_attr "type" "vecperm")])
 
+(define_expand "p9_xxbrd_v2df"
+  [(use (match_operand:V2DF 0 "vsx_register_operand" "=wa"))
+   (use (match_operand:V2DF 1 "vsx_register_operand" "wa"))]
+  "TARGET_P9_VECTOR"
+{
+  rtx op0 = gen_reg_rtx (V2DImode);
+  rtx op1 = gen_lowpart (V2DImode, operands[1]);
+  emit_insn (gen_p9_xxbrd_v2di (op0, op1));
+  emit_move_insn (operands[0], gen_lowpart (V2DFmode, op0));
+  DONE;
+})
+
 ;; Swap all bytes in each 32-bit element
-(define_insn "p9_xxbrw_<mode>"
-  [(set (match_operand:VSX_W 0 "vsx_register_operand" "=wa")
-	(bswap:VSX_W (match_operand:VSX_W 1 "vsx_register_operand" "wa")))]
+(define_insn "p9_xxbrw_v4si"
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
+	(bswap:V4SI (match_operand:V4SI 1 "vsx_register_operand" "wa")))]
   "TARGET_P9_VECTOR"
   "xxbrw %x0,%x1"
   [(set_attr "type" "vecperm")])
 
+(define_expand "p9_xxbrw_v4sf"
+  [(use (match_operand:V4SF 0 "vsx_register_operand" "=wa"))
+   (use (match_operand:V4SF 1 "vsx_register_operand" "wa"))]
+  "TARGET_P9_VECTOR"
+{
+  rtx op0 = gen_reg_rtx (V4SImode);
+  rtx op1 = gen_lowpart (V4SImode, operands[1]);
+  emit_insn (gen_p9_xxbrw_v4si (op0, op1));
+  emit_move_insn (operands[0], gen_lowpart (V4SFmode, op0));
+  DONE;
+})
+
 ;; Swap all bytes in each element of vector
 (define_expand "revb_<mode>"
-  [(set (match_operand:VEC_REVB 0 "vsx_register_operand")
-	(bswap:VEC_REVB (match_operand:VEC_REVB 1 "vsx_register_operand")))]
+  [(use (match_operand:VEC_REVB 0 "vsx_register_operand"))
+   (use (match_operand:VEC_REVB 1 "vsx_register_operand"))]
   ""
 {
   if (TARGET_P9_VECTOR)
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 4536b53..64018db 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-02-09  Jakub Jelinek  <jakub@redhat.com>
+
+	PR target/84226
+	* gcc.target/powerpc/pr84226.c: New test.
+
 2018-02-09  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* gcc.target/powerpc/builtins-1-be.c <vclzb>: Rename duplicate test
diff --git a/gcc/testsuite/gcc.target/powerpc/pr84226.c b/gcc/testsuite/gcc.target/powerpc/pr84226.c
new file mode 100644
index 0000000..aae922b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr84226.c
@@ -0,0 +1,6 @@
+/* PR target/84226 */
+/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mpower9-misc -O1" } */
+
+#include "builtins-revb-runnable.c"