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| author | Jan Beulich <jbeulich@suse.com> | 2023-06-20 09:05:48 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2023-06-20 09:05:48 +0200 |
| commit | d3a21558fda9da3ce094ea6ecd331ced07e9c6fb (patch) | |
| tree | 07acde629299e76b0d0df0eaa339c8705e293410 | |
| parent | 963f87f8a65ec82f503ac4334a3da83b0a8a43b2 (diff) | |
| download | gcc-d3a21558fda9da3ce094ea6ecd331ced07e9c6fb.zip gcc-d3a21558fda9da3ce094ea6ecd331ced07e9c6fb.tar.gz gcc-d3a21558fda9da3ce094ea6ecd331ced07e9c6fb.tar.bz2 | |
x86: correct and improve "*vec_dupv2di"
The input constraint for the %vmovddup alternative was wrong, as the
upper 16 XMM registers require AVX512VL to be used with this insn. To
compensate, introduce a new alternative permitting all 32 registers, by
broadcasting to the full 512 bits in that case if AVX512VL is not
available.
gcc/
* config/i386/sse.md (vec_dupv2di): Correct %vmovddup input
constraint. Add new AVX512F alternative.
gcc/testsuite/
* gcc.target/i386/avx512f-dupv2di.c: New test.
| -rw-r--r-- | gcc/config/i386/sse.md | 28 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c | 13 |
2 files changed, 35 insertions, 6 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 8757035..b99becb 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -26162,19 +26162,35 @@ (symbol_ref "true")))]) (define_insn "*vec_dupv2di" - [(set (match_operand:V2DI 0 "register_operand" "=x,v,v,x") + [(set (match_operand:V2DI 0 "register_operand" "=x,v,v,v,x") (vec_duplicate:V2DI - (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,0")))] + (match_operand:DI 1 "nonimmediate_operand" " 0,Yv,vm,Yvm,0")))] "TARGET_SSE" "@ punpcklqdq\t%0, %0 vpunpcklqdq\t{%d1, %0|%0, %d1} + * return TARGET_AVX512VL ? \"vpbroadcastq\t{%1, %0|%0, %1}\" : \"vpbroadcastq\t{%1, %g0|%g0, %1}\"; %vmovddup\t{%1, %0|%0, %1} movlhps\t%0, %0" - [(set_attr "isa" "sse2_noavx,avx,sse3,noavx") - (set_attr "type" "sselog1,sselog1,sselog1,ssemov") - (set_attr "prefix" "orig,maybe_evex,maybe_vex,orig") - (set_attr "mode" "TI,TI,DF,V4SF")]) + [(set_attr "isa" "sse2_noavx,avx,avx512f,sse3,noavx") + (set_attr "type" "sselog1,sselog1,ssemov,sselog1,ssemov") + (set_attr "prefix" "orig,maybe_evex,evex,maybe_vex,orig") + (set (attr "mode") + (cond [(and (eq_attr "alternative" "2") + (match_test "!TARGET_AVX512VL")) + (const_string "XI") + (eq_attr "alternative" "3") + (const_string "DF") + (eq_attr "alternative" "4") + (const_string "V4SF") + ] + (const_string "TI"))) + (set (attr "enabled") + (if_then_else + (eq_attr "alternative" "2") + (symbol_ref "TARGET_AVX512VL + || (TARGET_AVX512F && !TARGET_PREFER_AVX256)") + (const_string "*")))]) (define_insn "avx2_vbroadcasti128_<mode>" [(set (match_operand:VI_256 0 "register_operand" "=x,v,v") diff --git a/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c b/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c new file mode 100644 index 0000000..d8d9609 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-dupv2di.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512f -mno-avx512vl -O2" } */ +/* { dg-final { scan-assembler-not "vmovddup\[^\n\]*%xmm16" } } */ + +typedef long long __attribute__ ((vector_size (16))) v2di; + +v2di bcst (long long ll) +{ + register long long x asm ("xmm16") = ll; + + asm ("" : "+v" (x)); + return (v2di) {x, x}; +} |