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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:26 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@linux-mips.org> | 2020-12-05 18:26:26 +0000 |
| commit | d38f8441bed01127358d46196aea2a2f55d0c949 (patch) | |
| tree | 663e80b995a2f2e26500effb77105eb6fd89d420 | |
| parent | 0a9ea215f7400612f6dae2c77351e503798ea599 (diff) | |
| download | gcc-d38f8441bed01127358d46196aea2a2f55d0c949.zip gcc-d38f8441bed01127358d46196aea2a2f55d0c949.tar.gz gcc-d38f8441bed01127358d46196aea2a2f55d0c949.tar.bz2 | |
VAX: Fix predicates and constraints for bit-field comparison insns
It makes no sense for insn operand predicates, as long as they accept a
register operand, to be more restrictive than the set of the associated
constraints, because expand will choose the insn based on the relevant
operand being a pseudo register then and reload keep it happily as a
memory reference if a constraint permits it. So the restriction posed
by such a predicate will be happily ignored, and moreover if a splitter
is added, such as required for MODE_CC support, the new instructions
will reject the original operands supplied, causing an ICE. An actual
example will be given with a subsequent change.
Therefore, similarly to EXTV/EXTZV/INSV insns, remove inconsistencies
with predicates and constraints of bit-field comparison insns, observing
that a bit-field located in memory is byte-addressed by the respective
machine instructions and therefore SImode may only be used with a
register or an offsettable memory operand (i.e. not an indexed,
pre-decremented, or post-incremented one).
Also give the insns names, for easier reference here and elsewhere.
gcc/
* config/vax/vax.md (*cmpv_2): Name insn.
(*cmpv, *cmpzv, *cmpzv_2): Likewise. Fix location predicate and
constraint.
| -rw-r--r-- | gcc/config/vax/vax.md | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md index d8774cd..34fdf67 100644 --- a/gcc/config/vax/vax.md +++ b/gcc/config/vax/vax.md @@ -853,20 +853,20 @@ ;; Register and non-offsettable-memory SImode cases of bit-field insns. -(define_insn "" +(define_insn "*cmpv" [(set (cc0) (compare - (sign_extract:SI (match_operand:SI 0 "register_operand" "r") + (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") (match_operand:QI 1 "general_operand" "g") (match_operand:SI 2 "general_operand" "nrmT")) (match_operand:SI 3 "general_operand" "nrmT")))] "" "cmpv %2,%1,%0,%3") -(define_insn "" +(define_insn "*cmpzv" [(set (cc0) (compare - (zero_extract:SI (match_operand:SI 0 "register_operand" "r") + (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") (match_operand:QI 1 "general_operand" "g") (match_operand:SI 2 "general_operand" "nrmT")) (match_operand:SI 3 "general_operand" "nrmT")))] @@ -921,7 +921,7 @@ ;; nonimmediate_operand is used to make sure that mode-ambiguous cases ;; don't match these (and therefore match the cases above instead). -(define_insn "" +(define_insn "*cmpv_2" [(set (cc0) (compare (sign_extract:SI (match_operand:QI 0 "memory_operand" "m") @@ -931,10 +931,10 @@ "" "cmpv %2,%1,%0,%3") -(define_insn "" +(define_insn "*cmpzv_2" [(set (cc0) (compare - (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") + (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") (match_operand:QI 1 "general_operand" "g") (match_operand:SI 2 "general_operand" "nrmT")) (match_operand:SI 3 "general_operand" "nrmT")))] |