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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-12-05 13:02:24 +0100 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-15 09:56:45 +0100 |
| commit | d328d3a6f8756ed61b3cdf3675b24051f7d3b2ef (patch) | |
| tree | d5eb64d284dd836617d70165d2d5420006123b8d | |
| parent | b77c32273b432db3f04175b95143b3ed5214f6f3 (diff) | |
| download | gcc-d328d3a6f8756ed61b3cdf3675b24051f7d3b2ef.zip gcc-d328d3a6f8756ed61b3cdf3675b24051f7d3b2ef.tar.gz gcc-d328d3a6f8756ed61b3cdf3675b24051f7d3b2ef.tar.bz2 | |
riscv: thead: Add support for the XTheadBs ISA extension
This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
* config/riscv/thead.md (*th_tst<mode>3): New INSN.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbs-tst.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | gcc/config/riscv/riscv.cc | 4 | ||||
| -rw-r--r-- | gcc/config/riscv/thead.md | 11 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 |
3 files changed, 26 insertions, 2 deletions
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index c91fa31..69fb789 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2412,8 +2412,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } - /* bext pattern for zbs. */ - if (TARGET_ZBS && outer_code == SET + /* bit extraction pattern (zbs:bext, xtheadbs:tst). */ + if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET && GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) == 1) { diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index 2da5aaee..3842a19 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -29,3 +29,14 @@ "th.addsl\t%0,%3,%1,%2" [(set_attr "type" "bitmanip") (set_attr "mode" "<X:MODE>")]) + +;; XTheadBs + +(define_insn "*th_tst<mode>3" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand 2 "const_int_operand" "n")))] + "TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)" + "th.tst\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c new file mode 100644 index 0000000..674cec0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +long +foo1 (long i) +{ + return 1L & (i >> 20); +} + +/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ |