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| author | H.J. Lu <hongjiu.lu@intel.com> | 2019-05-15 15:08:04 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2019-05-15 08:08:04 -0700 |
| commit | d0e9bf2a6db4df95b776c5bcd728f0e159116659 (patch) | |
| tree | ce6b5556c5b88e16295926c8b585e52c897b7af8 | |
| parent | 3fdce4b1ef47f305cd90e62905b4adc8a13a73c5 (diff) | |
| download | gcc-d0e9bf2a6db4df95b776c5bcd728f0e159116659.zip gcc-d0e9bf2a6db4df95b776c5bcd728f0e159116659.tar.gz gcc-d0e9bf2a6db4df95b776c5bcd728f0e159116659.tar.bz2 | |
i386: Emulate MMX mmx_pmaddwd with SSE
Emulate MMX pmaddwd with SSE. Only SSE register source operand is
allowed.
PR target/89021
* config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE.
(*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support.
From-SVN: r271220
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/mmx.md | 25 |
2 files changed, 21 insertions, 10 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7b2a9bb..597ba81 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,6 +1,12 @@ 2019-05-15 H.J. Lu <hongjiu.lu@intel.com> PR target/89021 + * config/i386/mmx.md (mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. + (*mmx_pmaddwd): Also allow TARGET_MMX_WITH_SSE. Add SSE support. + +2019-05-15 H.J. Lu <hongjiu.lu@intel.com> + + PR target/89021 * config/i386/mmx.md (mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. (*mmx_smulv4hi3_highpart): Also allow TARGET_MMX_WITH_SSE. Add diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d7c3bd4..7cbca96 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -835,11 +835,11 @@ (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand") + (match_operand:V4HI 1 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand") + (match_operand:V4HI 2 "register_mmxmem_operand") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -848,20 +848,20 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX" + "TARGET_MMX || TARGET_MMX_WITH_SSE" "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);") (define_insn "*mmx_pmaddwd" - [(set (match_operand:V2SI 0 "register_operand" "=y") + [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") (plus:V2SI (mult:V2SI (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 1 "nonimmediate_operand" "%0") + (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2SI (vec_select:V2HI - (match_operand:V4HI 2 "nonimmediate_operand" "ym") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv") (parallel [(const_int 0) (const_int 2)])))) (mult:V2SI (sign_extend:V2SI @@ -870,10 +870,15 @@ (sign_extend:V2SI (vec_select:V2HI (match_dup 2) (parallel [(const_int 1) (const_int 3)]))))))] - "TARGET_MMX && ix86_binary_operator_ok (MULT, V4HImode, operands)" - "pmaddwd\t{%2, %0|%0, %2}" - [(set_attr "type" "mmxmul") - (set_attr "mode" "DI")]) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && ix86_binary_operator_ok (MULT, V4HImode, operands)" + "@ + pmaddwd\t{%2, %0|%0, %2} + pmaddwd\t{%2, %0|%0, %2} + vpmaddwd\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxmul,sseiadd,sseiadd") + (set_attr "mode" "DI,TI,TI")]) (define_expand "mmx_pmulhrwv4hi3" [(set (match_operand:V4HI 0 "register_operand") |