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| author | Richard Kenner <kenner@gcc.gnu.org> | 1992-04-22 18:56:12 -0400 |
|---|---|---|
| committer | Richard Kenner <kenner@gcc.gnu.org> | 1992-04-22 18:56:12 -0400 |
| commit | cd2b37d9f7d7ea299d071d64641bc3ae105fa808 (patch) | |
| tree | 78a9ef87209833d53c225d49936d73ad8198ec37 | |
| parent | 878e0c14c4eb4367b849edc896d914b00687aa59 (diff) | |
| download | gcc-cd2b37d9f7d7ea299d071d64641bc3ae105fa808.zip gcc-cd2b37d9f7d7ea299d071d64641bc3ae105fa808.tar.gz gcc-cd2b37d9f7d7ea299d071d64641bc3ae105fa808.tar.bz2 | |
*** empty log message ***
From-SVN: r819
| -rw-r--r-- | gcc/config/rs6000/rs6000.c | 16 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.h | 2 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 1274 |
3 files changed, 646 insertions, 646 deletions
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index e190d80..2e0fb88 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -113,7 +113,7 @@ non_short_cint_operand (op, mode) ctr, or lr). */ int -gen_reg_operand (op, mode) +gpc_reg_operand (op, mode) register rtx op; enum machine_mode mode; { @@ -147,7 +147,7 @@ reg_or_short_operand (op, mode) if (GET_CODE (op) == CONST_INT) return short_cint_operand (op, mode); - return gen_reg_operand (op, mode); + return gpc_reg_operand (op, mode); } /* Similar, except check if the negation of the constant would be valid for @@ -161,7 +161,7 @@ reg_or_neg_short_operand (op, mode) if (GET_CODE (op) == CONST_INT) return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P'); - return gen_reg_operand (op, mode); + return gpc_reg_operand (op, mode); } /* Return 1 if the operand is either a register or an integer whose high-order @@ -176,7 +176,7 @@ reg_or_u_short_operand (op, mode) && (INTVAL (op) & 0xffff0000) == 0) return 1; - return gen_reg_operand (op, mode); + return gpc_reg_operand (op, mode); } /* Return 1 is the operand is either a non-special register or ANY @@ -187,7 +187,7 @@ reg_or_cint_operand (op, mode) register rtx op; enum machine_mode mode; { - return GET_CODE (op) == CONST_INT || gen_reg_operand (op, mode); + return GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode); } /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a @@ -279,7 +279,7 @@ logical_operand (op, mode) register rtx op; enum machine_mode mode; { - return (gen_reg_operand (op, mode) + return (gpc_reg_operand (op, mode) || (GET_CODE (op) == CONST_INT && ((INTVAL (op) & 0xffff0000) == 0 || (INTVAL (op) & 0xffff) == 0))); @@ -364,7 +364,7 @@ reg_or_mem_operand (op, mode) register rtx op; register enum machine_mode mode; { - return gen_reg_operand (op, mode) || memory_operand (op, mode); + return gpc_reg_operand (op, mode) || memory_operand (op, mode); } /* Return 1 if the operand, used inside a MEM, is a valid first argument @@ -397,7 +397,7 @@ input_operand (op, mode) is valid. */ if (GET_MODE_CLASS (mode) == MODE_FLOAT || GET_MODE_SIZE (mode) > UNITS_PER_WORD) - return gen_reg_operand (op, mode); + return gpc_reg_operand (op, mode); /* The only cases left are integral modes one word or smaller (we do not get called for MODE_CC values). These can be in any diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index d639807..260c52c 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -1806,7 +1806,7 @@ toc_section () \ {"short_cint_operand", {CONST_INT}}, \ {"u_short_cint_operand", {CONST_INT}}, \ {"non_short_cint_operand", {CONST_INT}}, \ - {"gen_reg_operand", {SUBREG, REG}}, \ + {"gpc_reg_operand", {SUBREG, REG}}, \ {"cc_reg_operand", {SUBREG, REG}}, \ {"reg_or_short_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_neg_short_operand", {SUBREG, REG, CONST_INT}}, \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 39de456..775d8fc 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -48,13 +48,13 @@ ;; complex forms. Basic data transfer is done later. (define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -64,7 +64,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -73,22 +73,22 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" "andil. %0,%1,255" [(set_attr "type" "compare")]) (define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "gen_reg_operand" "") - (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))] + [(set (match_operand:HI 0 "gpc_reg_operand" "") + (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:HI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -97,13 +97,13 @@ [(set_attr "type" "load,*")]) (define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "r") - (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "r") + (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -113,7 +113,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -122,22 +122,22 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" "andil. %0,%1,65535" [(set_attr "type" "compare")]) (define_expand "extendhisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -147,7 +147,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -156,9 +156,9 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_dup 1)))] "" "exts. %0,%1" @@ -166,8 +166,8 @@ ;; Fixed-point arithmetic insns. (define_insn "addsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") (match_operand:SI 2 "add_operand" "rI,J")))] "" "@ @@ -176,7 +176,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -186,10 +186,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" "a%I2. %0,%1,%2" @@ -200,8 +200,8 @@ ;; add should be last in case the result gets used in an address. (define_split - [(set (match_operand:SI 0 "gen_reg_operand" "") - (plus:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "non_add_cint_operand" "")))] "" [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) @@ -219,15 +219,15 @@ }") (define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "sfi %0,%1,-1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") - (match_operand:SI 2 "gen_reg_operand" "r,r")))] + (match_operand:SI 2 "gpc_reg_operand" "r,r")))] "" "@ sf %0,%2,%1 @@ -235,8 +235,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -245,17 +245,17 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "" "sf. %0,%2,%1" [(set_attr "type" "compare")]) (define_expand "subsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] "" @@ -275,11 +275,11 @@ (define_expand "sminsi3" [(set (match_dup 3) - (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "") + (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] "" " @@ -287,47 +287,47 @@ (define_expand "smaxsi3" [(set (match_dup 3) - (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "") + (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] "" " { operands[3] = gen_reg_rtx (SImode); }") (define_expand "uminsi3" - [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -2147483648))) - (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "") + (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (const_int -2147483648))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] "" " { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") (define_expand "umaxsi3" - [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -2147483648))) - (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "") + (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (const_int -2147483648))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] "" " { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))))] @@ -337,7 +337,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) @@ -350,12 +350,12 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (if_then_else:SI (gt (match_dup 1) (match_dup 2)) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))))] @@ -366,26 +366,26 @@ ;; We don't need abs with condition code because such comparisons should ;; never be done. (define_insn "abssi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "abs %0,%1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] "" "nabs %0,%1") (define_insn "negsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "neg %0,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -394,9 +394,9 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (neg:SI (match_dup 1)))] "" "neg. %0,%1" @@ -423,8 +423,8 @@ [(set_attr "type" "compare")]) (define_insn "mulsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) (clobber (match_scratch:SI 3 "=q,q"))] "" @@ -434,8 +434,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r")) (clobber (match_scratch:SI 4 "=q"))] @@ -445,10 +445,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (mult:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q"))] "" @@ -460,10 +460,10 @@ ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). (define_insn "divmodsi4" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r"))) - (set (match_operand:SI 3 "gen_reg_operand" "=q") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) + (set (match_operand:SI 3 "gpc_reg_operand" "=q") (mod:SI (match_dup 1) (match_dup 2)))] "" "divs %0,%1,%2") @@ -471,8 +471,8 @@ ;; For powers of two we can do srai/aze for divide and then adjust for ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used. (define_expand "divsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (div:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] "" " @@ -484,11 +484,11 @@ (define_expand "modsi3" [(set (match_dup 3) - (div:SI (match_operand:SI 1 "gen_reg_operand" "") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" ""))) (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5))) (clobber (scratch:SI))]) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 1) (match_dup 4)))] "" " @@ -504,15 +504,15 @@ }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N")))] "exact_log2 (INTVAL (operands[2])) >= 0" "srai %0,%1,%p2\;aze %0,%0") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N"))) (clobber (match_scratch:SI 3 "=r"))] "exact_log2 (INTVAL (operands[2])) >= 0" @@ -521,22 +521,22 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (div:SI (match_dup 1) (match_dup 2)))] "exact_log2 (INTVAL (operands[2])) >= 0" "srai %0,%1,%p2\;aze. %0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (udiv:SI (plus:DI (lshift:DI - (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) + (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 32)) (zero_extend:DI (match_operand:SI 2 "register_operand" "*q"))) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (set (match_operand:SI 4 "register_operand" "=*q") (umod:SI (plus:DI (lshift:DI @@ -587,10 +587,10 @@ }") (define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") - (udiv:SI (match_operand:SI 1 "gen_reg_operand" "") + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") + (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" ""))) - (set (match_operand:SI 3 "gen_reg_operand" "") + (set (match_operand:SI 3 "gpc_reg_operand" "") (umod:SI (match_dup 1) (match_dup 2)))])] "" " @@ -616,8 +616,8 @@ }") (define_insn "andsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "?r,L,K,J"))) (clobber (match_scratch:CC 3 "=X,X,x,x"))] "" @@ -629,7 +629,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] @@ -643,10 +643,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (and:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -661,8 +661,8 @@ ;; since this need not be done as combine will do it. (define_split - [(set (match_operand:SI 0 "gen_reg_operand" "") - (and:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "non_and_cint_operand" "")))] "" [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) @@ -697,8 +697,8 @@ }") (define_insn "iorsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r") - (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ @@ -708,8 +708,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -718,10 +718,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (match_dup 1) (match_dup 2)))] "" "or. %0,%1,%2" @@ -731,8 +731,8 @@ ;; does one 16-bit part. This is used by combine. (define_split - [(set (match_operand:SI 0 "gen_reg_operand" "") - (ior:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "non_logical_cint_operand" "")))] "" [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) @@ -745,8 +745,8 @@ }") (define_insn "xorsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r") - (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ @@ -756,8 +756,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -766,10 +766,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (xor:SI (match_dup 1) (match_dup 2)))] "" "xor. %0,%1,%2" @@ -779,8 +779,8 @@ ;; does one 16-bit part. This is used by combine. (define_split - [(set (match_operand:SI 0 "gen_reg_operand" "") - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "non_logical_cint_operand" "")))] "" [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) @@ -793,16 +793,16 @@ }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "eqv %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -811,26 +811,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" "eqv. %0,%1,%2" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "andc %0,%2,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -839,26 +839,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_dup 1)) (match_dup 2)))] "" "andc. %0,%2,%1" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "orc %0,%2,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -867,26 +867,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] "" "orc. %0,%2,%1" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nand %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -895,26 +895,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" "nand. %0,%1,%2" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nor %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -923,10 +923,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" "nor. %0,%1,%2" @@ -937,50 +937,50 @@ ;; would modify an input register. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0")) (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r"))))] + (match_operand:SI 3 "gpc_reg_operand" "r"))))] "" "maskir %0,%3,%1") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_operand:SI 3 "gen_reg_operand" "r") + (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_dup 1))))] "" "maskir %0,%3,%1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))))] + (match_operand:SI 3 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0"))))] "" "maskir %0,%3,%1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))))] + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0"))))] "" "maskir %0,%3,%1") (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) + (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0")) (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) (and:SI (match_dup 1) (match_dup 3))))] "" @@ -990,9 +990,9 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_operand:SI 3 "gen_reg_operand" "r") + (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_dup 1))) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") @@ -1006,11 +1006,11 @@ [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (ior:SI (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))) + (match_operand:SI 3 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_dup 1) (match_dup 3)) (and:SI (not:SI (match_dup 1)) (match_dup 2))))] "" @@ -1020,12 +1020,12 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r") + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))) + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "0"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (and:SI (match_dup 3) (match_dup 1)) (and:SI (not:SI (match_dup 1)) (match_dup 2))))] "" @@ -1035,10 +1035,10 @@ ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. (define_insn "insv" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:SI 3 "gen_reg_operand" "r"))] + (match_operand:SI 3 "gpc_reg_operand" "r"))] "" "* { @@ -1051,8 +1051,8 @@ }") (define_insn "extzv" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")))] "" @@ -1070,7 +1070,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) @@ -1108,11 +1108,11 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] "" "* @@ -1135,15 +1135,15 @@ [(set_attr "type" "delayed_compare")]) (define_insn "rotlsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "" "rl%I2nm %0,%1,%h2,0,31") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1153,18 +1153,18 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_dup 1) (match_dup 2)))] "" "rl%I2nm. %0,%1,%h2,0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")))] "" @@ -1173,7 +1173,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1185,21 +1185,21 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "rl%I2nm. %0,%1,%h2,%m3,%M3" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" "rl%I2nm %0,%1,%h2,24,31") @@ -1208,7 +1208,7 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1220,20 +1220,20 @@ [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "rl%I2nm. %0,%1,%h2,24,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" "rl%I2nm %0,%1,%h2,16,31") @@ -1242,7 +1242,7 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1254,10 +1254,10 @@ [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "rl%I2nm. %0,%1,%h2,16,31" @@ -1267,8 +1267,8 @@ ;; SHIFT_COUNT_TRUNCATED. (define_insn "ashlsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" @@ -1278,7 +1278,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1291,10 +1291,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" @@ -1304,8 +1304,8 @@ [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")))] "includes_lshift_p (operands[2], operands[3])" @@ -1314,7 +1314,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1326,11 +1326,11 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_lshift_p (operands[2], operands[3])" "rlinm. %0,%h1,%h2,%m3,%M3" @@ -1339,8 +1339,8 @@ ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as ;; "sli x,x,0". (define_insn "lshrsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" @@ -1350,7 +1350,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1363,10 +1363,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (lshiftrt:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" @@ -1376,8 +1376,8 @@ [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")))] "includes_rshift_p (operands[2], operands[3])" @@ -1386,7 +1386,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1398,21 +1398,21 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_rshift_p (operands[2], operands[3])" "rlinm. %0,%1,%s2,%m3,%M3" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "rlinm %0,%1,%s2,24,31") @@ -1422,7 +1422,7 @@ (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1435,20 +1435,20 @@ (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "rlinm. %0,%1,%s2,24,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "rlinm %0,%1,%s2,16,31") @@ -1458,7 +1458,7 @@ (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1471,46 +1471,46 @@ (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "rlinm. %0,%1,%s2,16,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 31)))] "" "rrib %0,%1,%2") (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 31)))] "" "rrib %0,%1,%2") (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 1) (const_int 0)))] "" "rrib %0,%1,%2") (define_insn "ashrsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" @@ -1520,7 +1520,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1533,10 +1533,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashiftrt:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" @@ -1547,10 +1547,10 @@ (define_expand "extendqisi2" [(parallel [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") + (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (clobber (scratch:SI))]) - (parallel [(set (match_operand:SI 0 "gen_reg_operand" "") + (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24))) (clobber (scratch:SI))])] @@ -1561,10 +1561,10 @@ (define_expand "extendqihi2" [(parallel [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") + (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (clobber (scratch:SI))]) - (parallel [(set (match_operand:HI 0 "gen_reg_operand" "") + (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24))) (clobber (scratch:SI))])] @@ -1589,8 +1589,8 @@ ;; is not guaranteed. Perhaps this should be tightened up at some point. (define_insn "extendsfdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "* { @@ -1602,8 +1602,8 @@ [(set_attr "type" "fp")]) (define_insn "truncdfsf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "* { @@ -1615,179 +1615,179 @@ [(set_attr "type" "fp")]) (define_insn "negsf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "fneg %0,%1" [(set_attr "type" "fp")]) (define_insn "abssf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] "" "fnabs %0,%1" [(set_attr "type" "fp")]) (define_insn "addsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fa %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "subsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (minus:SF (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fs %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "mulsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fm %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "divsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (div:SF (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fd %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] "" "fma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] "" "fms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f"))))] "" "fnma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f"))))] "" "fnms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "negdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "fneg %0,%1" [(set_attr "type" "fp")]) (define_insn "absdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] "" "fnabs %0,%1" [(set_attr "type" "fp")]) (define_insn "adddf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fa %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "subdf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (minus:DF (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fs %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "muldf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fm %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "divdf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (div:DF (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fd %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f")))] "" "fma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f")))] "" "fms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f"))))] "" "fnma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f"))))] "" "fnms %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -1796,10 +1796,10 @@ (define_expand "floatsidf2" [(set (match_dup 2) (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_dup 3))) (match_dup 4))) - (set (match_operand:DF 0 "gen_reg_operand" "") + (set (match_operand:DF 0 "gpc_reg_operand" "") (minus:DF (subreg:DF (match_dup 2) 0) (match_dup 5)))] "" @@ -1820,9 +1820,9 @@ (define_expand "floatunssidf2" [(set (match_dup 2) - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (match_dup 3))) - (set (match_operand:DF 0 "gen_reg_operand" "") + (set (match_operand:DF 0 "gpc_reg_operand" "") (minus:DF (subreg:DF (match_dup 2) 0) (match_dup 4)))] "" @@ -1841,9 +1841,9 @@ ;; For the above two cases, we always split. (define_split - [(set (match_operand:DI 0 "gen_reg_operand" "") + [(set (match_operand:DI 0 "gpc_reg_operand" "") (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "logical_operand" ""))) (match_operand:DI 3 "immediate_operand" "")))] "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD @@ -1858,9 +1858,9 @@ }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "logical_operand" "rKJ"))) (match_operand:DI 3 "immediate_operand" "n")))] "HOST_BITS_PER_INT == BITS_PER_WORD @@ -1869,8 +1869,8 @@ "#") (define_split - [(set (match_operand:DI 0 "gen_reg_operand" "=") - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) + [(set (match_operand:DI 0 "gpc_reg_operand" "=") + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (match_operand:DI 2 "immediate_operand" "")))] "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD && GET_CODE (operands[2]) == CONST_DOUBLE @@ -1890,8 +1890,8 @@ }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:DI 2 "immediate_operand" "n")))] "HOST_BITS_PER_INT == BITS_PER_WORD && GET_CODE (operands[2]) == CONST_DOUBLE @@ -1899,8 +1899,8 @@ "#") (define_expand "fix_truncdfsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -1910,8 +1910,8 @@ }") (define_expand "fixuns_truncdfsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -1941,12 +1941,12 @@ }") (define_expand "trunc_call_rtl" - [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" "")) + [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) (use (reg:DF 33)) (parallel [(set (reg:SI 3) (call (mem:SI (match_operand 2 "" "")) (const_int 0))) (clobber (scratch:SI))]) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (reg:SI 3))] "" " @@ -1957,29 +1957,29 @@ ;; Define the DImode operations that can be done in a small number ;; of instructions. (define_insn "adddi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r") - (match_operand:DI 2 "gen_reg_operand" "r")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "a %L0,%L1,%L2\;ae %0,%1,%2") (define_insn "subdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (minus:DI (match_operand:DI 1 "gen_reg_operand" "r") - (match_operand:DI 2 "gen_reg_operand" "r")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "sf %L0,%L2,%L1\;sfe %0,%2,%1") (define_insn "negdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] "" "sfi %L0,%L1,0\;sfze %0,%1") (define_insn "mulsidi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) - (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r")))) + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) (clobber (match_scratch:SI 3 "=q"))] "" "mul %0,%1,%2\;mfmq %L0") @@ -1988,8 +1988,8 @@ ;; operands 0 and 1 (the usual case) can be in the same register. That's ;; why we have the strange constraints below. (define_insn "ashldi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r") - (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") + (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (clobber (match_scratch:SI 3 "=X,q,q,q"))] "" @@ -2000,8 +2000,8 @@ sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2") (define_insn "lshrdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r") - (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") + (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (clobber (match_scratch:SI 3 "=X,q,q,q"))] "" @@ -2015,8 +2015,8 @@ ;; just handle shifts by constants. (define_expand "ashrdi3" - [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=") - (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "") + [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=") + (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (match_scratch:SI 3 ""))])] "" @@ -2026,8 +2026,8 @@ }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "M,i"))) (clobber (match_scratch:SI 3 "=X,q"))] "" @@ -2070,8 +2070,8 @@ (define_insn "" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l") (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))] - "gen_reg_operand (operands[0], SImode) - || gen_reg_operand (operands[1], SImode)" + "gpc_reg_operand (operands[0], SImode) + || gpc_reg_operand (operands[1], SImode)" "@ ai %0,%1,0 l%U1%X1 %0,%1 @@ -2085,9 +2085,9 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] "" "ai. %0,%1,0" [(set_attr "type" "compare")]) @@ -2108,8 +2108,8 @@ (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))] - "gen_reg_operand (operands[0], HImode) - || gen_reg_operand (operands[1], HImode)" + "gpc_reg_operand (operands[0], HImode) + || gpc_reg_operand (operands[1], HImode)" "@ oril %0,%1,0 lhz%U1%X1 %0,%1 @@ -2135,8 +2135,8 @@ (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))] - "gen_reg_operand (operands[0], QImode) - || gen_reg_operand (operands[1], QImode)" + "gpc_reg_operand (operands[0], QImode) + || gpc_reg_operand (operands[1], QImode)" "@ oril %0,%1,0 lbz%U1%X1 %0,%1 @@ -2260,7 +2260,7 @@ }") (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r") (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))] "REGNO (operands[0]) <= 31" "@ @@ -2269,7 +2269,7 @@ [(set_attr "type" "*,load")]) (define_split - [(set (match_operand:SF 0 "gen_reg_operand" "") + [(set (match_operand:SF 0 "gpc_reg_operand" "") (match_operand:SF 1 "easy_fp_constant" ""))] "reload_completed && REGNO (operands[0]) <= 31" [(set (match_dup 2) (match_dup 3))] @@ -2280,8 +2280,8 @@ (define_insn "" [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") (match_operand:SF 1 "input_operand" "f,m,f"))] - "gen_reg_operand (operands[0], SFmode) - || gen_reg_operand (operands[1], SFmode)" + "gpc_reg_operand (operands[0], SFmode) + || gpc_reg_operand (operands[1], SFmode)" "@ fmr %0,%1 lfs%U1%X1 %0,%1 @@ -2386,7 +2386,7 @@ }") (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=r,r") + [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r") (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))] "REGNO (operands[0]) <= 31" "@ @@ -2395,7 +2395,7 @@ [(set_attr "type" "*,load")]) (define_split - [(set (match_operand:DF 0 "gen_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "easy_fp_constant" ""))] "reload_completed && REGNO (operands[0]) <= 31" [(set (match_dup 2) (match_dup 3)) @@ -2409,8 +2409,8 @@ (define_insn "" [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m") (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))] - "gen_reg_operand (operands[0], DFmode) - || gen_reg_operand (operands[1], DFmode)" + "gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode)" "@ fmr %0,%1 lfd%U1%X1 %0,%1 @@ -2442,8 +2442,8 @@ (define_insn "" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") (match_operand:DI 1 "input_operand" "r,m,r"))] - "gen_reg_operand (operands[0], DImode) - || gen_reg_operand (operands[1], DImode)" + "gpc_reg_operand (operands[0], DImode) + || gpc_reg_operand (operands[1], DImode)" "* { switch (which_alternative) @@ -2507,8 +2507,8 @@ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] - "gen_reg_operand (operands[0], TImode) - || gen_reg_operand (operands[1], TImode)" + "gpc_reg_operand (operands[0], TImode) + || gpc_reg_operand (operands[1], TImode)" "* { switch (which_alternative) @@ -2590,7 +2590,7 @@ (define_insn "" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "gen_reg_operand" "=r") + [(set (match_operand:SI 1 "gpc_reg_operand" "=r") (match_operand:SI 2 "indirect_operand" "Q"))])] "" "* @@ -2663,7 +2663,7 @@ (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "indirect_operand" "=Q") - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (clobber (match_scratch:SI 3 "=q"))])] "" "stsi %2,%P1,%O0") @@ -2678,10 +2678,10 @@ ;; that will benefit the most). (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") - (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") + (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2690,10 +2690,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2701,10 +2701,10 @@ stu %3,%2(%1)") (define_insn "" - [(set (match_operand:HI 3 "gen_reg_operand" "=r,r") - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2713,11 +2713,11 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (zero_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2726,11 +2726,11 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (sign_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2739,10 +2739,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:HI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:HI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2751,10 +2751,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:QI 3 "gen_reg_operand" "=r,r") - (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") + (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2763,11 +2763,11 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (zero_extend:SI - (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2776,10 +2776,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:QI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:QI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2787,10 +2787,10 @@ stbu %3,%2(%1)") (define_insn "" - [(set (match_operand:SF 3 "gen_reg_operand" "=f,f") - (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") + (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2799,10 +2799,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:SF 3 "gen_reg_operand" "f,f")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:SF 3 "gpc_reg_operand" "f,f")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2810,10 +2810,10 @@ frsp %3,%3\;stfsu %3,%2(%1)") (define_insn "" - [(set (match_operand:DF 3 "gen_reg_operand" "=f,f") - (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") + (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2822,10 +2822,10 @@ [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:DF 3 "gen_reg_operand" "f,f")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:DF 3 "gpc_reg_operand" "f,f")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -2864,8 +2864,8 @@ ;; operands[1] is the address of data area of the function to call (define_expand "call_via_ptr" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (mem:SI (match_operand:SI 1 "gen_reg_operand" ""))) + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) (reg:SI 2)) (set (reg:SI 2) @@ -2947,7 +2947,7 @@ ;; how it is used. (define_expand "cmpsi" [(set (cc0) - (compare (match_operand:SI 0 "gen_reg_operand" "") + (compare (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "reg_or_short_operand" "")))] "" " @@ -2965,8 +2965,8 @@ }") (define_expand "cmpsf" - [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "") - (match_operand:SF 1 "gen_reg_operand" "")))] + [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") + (match_operand:SF 1 "gpc_reg_operand" "")))] "" " { @@ -2977,8 +2977,8 @@ }") (define_expand "cmpdf" - [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "") - (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") + (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -3141,7 +3141,7 @@ ;; the cases we don't want to handle. (define_expand "seq" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (eq:SI (match_dup 2) (const_int 0)))] "" " @@ -3153,7 +3153,7 @@ (define_expand "sne" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ne:SI (match_dup 2) (const_int 0)))] "" " @@ -3168,7 +3168,7 @@ ;; A > 0 is best done using the portable sequence, so fail in that case. (define_expand "sgt" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (gt:SI (match_dup 2) (const_int 0)))] "" " @@ -3185,7 +3185,7 @@ ;; A < 0 is best done in the portable way for A an integer. (define_expand "slt" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (lt:SI (match_dup 2) (const_int 0)))] "" " @@ -3201,7 +3201,7 @@ (define_expand "sge" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 2) (const_int 0)))] "" " @@ -3214,7 +3214,7 @@ ;; A <= 0 is best done the portable way for A an integer. (define_expand "sle" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (le:SI (match_dup 2) (const_int 0)))] "" " @@ -3230,7 +3230,7 @@ (define_expand "sgtu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (gtu:SI (match_dup 2) (const_int 0)))] "" " @@ -3241,7 +3241,7 @@ (define_expand "sltu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ltu:SI (match_dup 2) (const_int 0)))] "" " @@ -3252,7 +3252,7 @@ (define_expand "sgeu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (geu:SI (match_dup 2) (const_int 0)))] "" " @@ -3263,7 +3263,7 @@ (define_expand "sleu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (leu:SI (match_dup 2) (const_int 0)))] "" " @@ -3275,7 +3275,7 @@ ;; Here are the actual compare insns. (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "cmp%I2 %0,%1,%2" @@ -3287,9 +3287,9 @@ (define_split [(set (match_operand:CC 0 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "non_short_cint_operand" ""))) - (clobber (match_operand:SI 3 "gen_reg_operand" ""))] + (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] "find_single_use (operands[0], insn, 0) && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" @@ -3311,7 +3311,7 @@ (define_insn "" [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] "" "cmpl%I2 %0,%1,%W2" @@ -3324,27 +3324,27 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=y") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "short_cint_operand" "i"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] "" "#") (define_insn "" [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "u_short_cint_operand" "i"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] "" "#") (define_split [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "short_cint_operand" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] "" [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) @@ -3352,9 +3352,9 @@ (define_split [(set (match_operand:CCUNS 3 "cc_reg_operand" "") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "u_short_cint_operand" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] "" [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) @@ -3362,16 +3362,16 @@ (define_insn "" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) (define_insn "" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -3384,7 +3384,7 @@ ;; cases the insns below which don't use an intermediate CR field will ;; be used instead. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]))] @@ -3397,14 +3397,14 @@ [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]) (const_int 0))) - (set (match_operand:SI 3 "gen_reg_operand" "=r") + (set (match_operand:SI 3 "gpc_reg_operand" "=r") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "" "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashift:SI (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]) @@ -3435,7 +3435,7 @@ (const_int 0)]) (match_operand:SI 3 "const_int_operand" "n")) (const_int 0))) - (set (match_operand:SI 4 "gen_reg_operand" "=r") + (set (match_operand:SI 4 "gpc_reg_operand" "=r") (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] "" @@ -3492,11 +3492,11 @@ ;; so it is useful to combine 2 scc instructions to use only one mfcr. (define_peephole - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)])) - (set (match_operand:SI 3 "gen_reg_operand" "=r") + (set (match_operand:SI 3 "gpc_reg_operand" "=r") (match_operator:SI 4 "scc_comparison_operator" [(match_operand 5 "cc_reg_operand" "y") (const_int 0)]))] @@ -3518,8 +3518,8 @@ ;; the cmp/mfcr sequence we would otherwise generate. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] "" @@ -3533,10 +3533,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") (compare:CC - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (eq:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] "" @@ -3549,10 +3549,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" "@ @@ -3566,9 +3566,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" @@ -3584,11 +3584,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" @@ -3601,8 +3601,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] "" "@ @@ -3614,11 +3614,11 @@ ;; This is what (plus (ne X (const_int 0)) Y) looks like. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "ai %3,%1,-1\;aze %0,%2") @@ -3627,9 +3627,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -3640,11 +3640,11 @@ [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] @@ -3653,8 +3653,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O"))) (clobber (match_scratch:SI 3 "=r,X"))] "" @@ -3665,10 +3665,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") (compare:CC - (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (le:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r,X"))] "" @@ -3678,10 +3678,10 @@ [(set_attr "type" "delayed_compare,compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -3691,9 +3691,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -3705,11 +3705,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -3719,8 +3719,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] "" "@ @@ -3728,8 +3728,8 @@ ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0") @@ -3737,20 +3737,20 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (leu:SI (match_dup 1) (match_dup 2)))] "" "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "sf%I2 %4,%1,%2\;aze %0,%3") @@ -3758,9 +3758,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3770,11 +3770,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3782,18 +3782,18 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4") @@ -3802,9 +3802,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3815,11 +3815,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3827,8 +3827,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31") @@ -3836,20 +3836,20 @@ (define_insn "" [(set (match_operand:SI 3 "cc_reg_operand" "=x") (compare:CC - (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (lt:SI (match_dup 1) (match_dup 2)))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3") @@ -3857,9 +3857,9 @@ (define_insn "" [(set (match_operand:SI 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3869,11 +3869,11 @@ (define_insn "" [(set (match_operand:SI 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3881,15 +3881,15 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] "" "@ @@ -3899,10 +3899,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ltu:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -3911,8 +3911,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] @@ -3926,7 +3926,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) (const_int 0))) @@ -3942,11 +3942,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] "" @@ -3958,8 +3958,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] "" "@ @@ -3967,8 +3967,8 @@ ai %0,%1,%n2\;sfe %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -3977,10 +3977,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ge:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -3988,10 +3988,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") @@ -3999,9 +3999,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4011,11 +4011,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4023,20 +4023,20 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") ;; This is (and (neg (ge X (const_int 0))) Y). (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "srai %3,%1,31\;andc %0,%2,%3") @@ -4046,9 +4046,9 @@ (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -4060,11 +4060,11 @@ (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) (const_int 31))) (match_dup 2))) @@ -4074,8 +4074,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] "" "@ @@ -4085,10 +4085,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (geu:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -4097,10 +4097,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -4110,9 +4110,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4124,11 +4124,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4138,8 +4138,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] "" "@ @@ -4147,11 +4147,11 @@ sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -4162,9 +4162,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4177,11 +4177,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4191,8 +4191,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)))] "" "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31") @@ -4200,18 +4200,18 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (const_int 0)))] "" "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")))] "" "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31") @@ -4219,20 +4219,20 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (match_dup 2)))] "" "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2") @@ -4240,9 +4240,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -4252,11 +4252,11 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -4264,10 +4264,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3") @@ -4275,9 +4275,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4287,11 +4287,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4299,22 +4299,22 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0))))] "" "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r"))))] "" "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0") @@ -4322,18 +4322,18 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gtu:SI (match_dup 1) (match_dup 2)))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I"))) (clobber (match_scratch:SI 4 "=&r,&r"))] @@ -4343,7 +4343,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I")) (const_int 0))) @@ -4355,11 +4355,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4367,8 +4367,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0") @@ -4525,11 +4525,11 @@ (define_split [(set (pc) (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gen_reg_operand" "") + [(match_operand:SI 1 "gpc_reg_operand" "") (const_int 1)]) (match_operand 5 "" "") (match_operand 6 "" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] @@ -4546,7 +4546,7 @@ (define_split [(set (pc) (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gen_reg_operand" "") + [(match_operand:SI 1 "gpc_reg_operand" "") (const_int 1)]) (match_operand 5 "" "") (match_operand 6 "" ""))) @@ -4554,7 +4554,7 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] - "reload_completed && ! gen_reg_operand (operands[0], SImode)" + "reload_completed && ! gpc_reg_operand (operands[0], SImode)" [(parallel [(set (match_dup 3) (compare:CC (plus:SI (match_dup 1) (const_int -1)) (const_int 0))) |