rx.md: updated "movsicc" expand to be matched by GCC

2018-02-09  Sebastian Perta  <sebastian.perta@renesas.com>

	*config/rx.md: updated "movsicc" expand to be matched by GCC
	*testsuite/gcc.target/rx/movsicc.c: new test case

From-SVN: r257533

3 files changed, 105 insertions, 1 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c42ffa6..7f19858 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-02-09  Sebastian Perta  <sebastian.perta@renesas.com>
+
+	*config/rx.md: updated "movsicc" expand to be matched by GCC
+	*testsuite/gcc.target/rx/movsicc.c: new test case
+
 2018-02-09  Peter Bergner  <bergner@vnet.ibm.com>
 
 	PR target/83926
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 35263b1..3fb2ac8 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -733,12 +733,17 @@
 (define_expand "movsicc"
   [(parallel
     [(set (match_operand:SI                  0 "register_operand")
-	  (if_then_else:SI (match_operand:SI 1 "comparison_operator")
+	  (if_then_else:SI (match_operand 1 "comparison_operator")
 			   (match_operand:SI 2 "nonmemory_operand")
 			   (match_operand:SI 3 "nonmemory_operand")))
      (clobber (reg:CC CC_REG))])]
   ""
 {
+  /* Make sure that we have an integer comparison...  */
+  if (GET_MODE (XEXP (operands[1], 0)) != CCmode
+      && GET_MODE (XEXP (operands[1], 0)) != SImode)
+    FAIL;
+
   /* One operand must be a constant or a register, the other must be a register.  */
   if (   ! CONSTANT_P (operands[2])
       && ! CONSTANT_P (operands[3])
diff --git a/gcc/testsuite/gcc.target/rx/movsicc.c b/gcc/testsuite/gcc.target/rx/movsicc.c
new file mode 100644
index 0000000..d8e6bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/rx/movsicc.c
@@ -0,0 +1,94 @@
+/* { dg-do compile } */
+/* { dg-options "-Os" } */
+
+typedef unsigned char u8;
+typedef unsigned short u16;
+signed int Xa, Xb;
+
+signed int stzreg_beq(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bne 1f" } } */
+
+signed int stzreg_bge(int i, int a, int b, int c)
+{
+  signed int x;
+  x = a;
+  if (i<c)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "blt 1f" } } */
+
+signed int stzreg_bgt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<10)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "ble 1f" } } */
+
+signed int stzreg_ble(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i>0)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bgt 1f" } } */
+
+signed int stzreg_blt(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (i<0)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "blt 1f" } } */
+
+signed int stzreg_bne(int i, int a, int b)
+{
+  signed int x;
+  x = a;
+  if (!i)
+    x = b;
+  return x;
+}
+
+/* { dg-final { scan-assembler "beq 1f" } } */
+
+signed int stzimm_le( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i>0)
+    x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "ble 1f" } } */
+
+signed int stzimm_le_r( int i, int a )
+{
+  signed int x;
+  x = a;
+  if (i<0)
+    x = 5;
+  return x;
+}
+
+/* { dg-final { scan-assembler "bge 1f" } } */