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author | Joern Rennecke <joern.rennecke@embecosm.com> | 2013-11-11 18:46:33 +0000 |
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committer | Joern Rennecke <amylaar@gcc.gnu.org> | 2013-11-11 18:46:33 +0000 |
commit | c733374a3d1ce1b1583baf023a7213c1dd6561b4 (patch) | |
tree | 4aec6ed058e2406f4292b817f6a25cc932d602fa | |
parent | 213dba3e31cf2ef2d14827ba34a224ff2ae7f6cf (diff) | |
download | gcc-c733374a3d1ce1b1583baf023a7213c1dd6561b4.zip gcc-c733374a3d1ce1b1583baf023a7213c1dd6561b4.tar.gz gcc-c733374a3d1ce1b1583baf023a7213c1dd6561b4.tar.bz2 |
forwprop-28.c: Adjust for ARC LOGICAL_OP_NON_SHORT_CIRCUIT definition.
* gcc.dg/tree-ssa/forwprop-28.c: Adjust for ARC
LOGICAL_OP_NON_SHORT_CIRCUIT definition.
* gcc.dg/tree-ssa/ssa-dom-thread-4.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise.
* gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise.
* gcc.dg/tree-ssa/vrp47.c: Likewise.
* gcc.dg/tree-ssa/vrp87.c: Likewise.
From-SVN: r204681
-rw-r--r-- | gcc/testsuite/ChangeLog | 12 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c | 5 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c | 2 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/vrp47.c | 4 | ||||
-rw-r--r-- | gcc/testsuite/gcc.dg/tree-ssa/vrp87.c | 2 |
9 files changed, 23 insertions, 10 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b7a8ff8..f58ee48 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2013-11-11 Joern Rennecke <joern.rennecke@embecosm.com> + + * gcc.dg/tree-ssa/forwprop-28.c: Adjust for ARC + LOGICAL_OP_NON_SHORT_CIRCUIT definition. + * gcc.dg/tree-ssa/ssa-dom-thread-4.c: Likewise. + * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c: Likewise. + * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c: Likewise. + * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c: Likewise. + * gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c: Likewise. + * gcc.dg/tree-ssa/vrp47.c: Likewise. + * gcc.dg/tree-ssa/vrp87.c: Likewise. + 2013-11-08 Joseph Myers <joseph@codesourcery.com> * gcc.dg/atomic/stdatomic-compare-exchange-1.c, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c index a64987b..06b406f 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/forwprop-28.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -fdump-tree-forwprop1" } */ extern char *frob (void); diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c index e97719f..fec3075 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-dom-thread-4.c @@ -61,7 +61,7 @@ bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b, zero. */ /* ARM Cortex-M0 defined LOGICAL_OP_NON_SHORT_CIRCUIT to false, so skip below test. */ -/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { { mips*-*-* avr-*-* } || { arm_cortex_m && arm_thumb1 } } } } } } */ +/* { dg-final { scan-tree-dump-times "Threaded" 3 "dom1" { target { ! { { mips*-*-* avr-*-* arc*-*-* } || { arm_cortex_m && arm_thumb1 } } } } } } */ /* MIPS defines LOGICAL_OP_NON_SHORT_CIRCUIT to 0, so we split both "a_elt || b_elt" and "b_elt && kill_elt" into two conditions each, rather than using "(var1 != 0) op (var2 != 0)". Also, as on other targets, @@ -81,8 +81,9 @@ bitmap_ior_and_compl (bitmap dst, const_bitmap a, const_bitmap b, -> "kill_elt->indx == b_elt->indx" in the second condition, skipping the known-true "b_elt && kill_elt" in the second condition. */ +/* Likewise for arc. */ /* For avr, BRANCH_COST is by default 0, so the default LOGICAL_OP_NON_SHORT_CIRCUIT definition also computes as 0. */ -/* { dg-final { scan-tree-dump-times "Threaded" 6 "dom1" { target mips*-*-* avr-*-* } } } */ +/* { dg-final { scan-tree-dump-times "Threaded" 6 "dom1" { target mips*-*-* avr-*-* arc*-*-* } } } */ /* { dg-final { cleanup-tree-dump "dom1" } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c index 56c936d..efc8a71 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -g -fdump-tree-optimized" } */ /* { dg-additional-options "-mbranch-cost=2" { target avr-*-* } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c index 8b87101..3be2310 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-4.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -g -fdump-tree-optimized" } */ /* { dg-additional-options "-mbranch-cost=2" { target avr-*-* } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c index 2aa225b..c22a0e0 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-5.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -g -fdump-tree-optimized" } */ /* { dg-additional-options "-mbranch-cost=2" { target avr-*-* } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c index 659e816..aa0970d 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-ccmp-6.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -g -fdump-tree-optimized" } */ /* { dg-additional-options "-mbranch-cost=2" { target avr-*-* } } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c index d8c5841..74b520b 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp47.c @@ -1,9 +1,9 @@ -/* Skip on MIPS, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc +/* Skip on MIPS/ARC, where LOGICAL_OP_NON_SHORT_CIRCUIT inhibits the setcc optimizations that expose the VRP opportunity. */ /* Skip on S/390 and avr. Lower values in BRANCH_COST lead to two conditional jumps when evaluating an && condition. VRP is not able to optimize this. */ -/* { dg-do compile { target { ! "mips*-*-* s390*-*-* avr-*-* mn10300-*-*" } } } */ +/* { dg-do compile { target { ! "mips*-*-* arc*-*-* s390*-*-* avr-*-* mn10300-*-*" } } } */ /* { dg-options "-O2 -fdump-tree-vrp1 -fdump-tree-dom1 -fdump-tree-vrp2" } */ /* { dg-additional-options "-march=i586" { target { { i?86-*-* x86_64-*-* } && ia32 } } } */ /* Skip on ARM Cortex-M0, where LOGICAL_OP_NON_SHORT_CIRCUIT is set to false, diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vrp87.c b/gcc/testsuite/gcc.dg/tree-ssa/vrp87.c index 7339823..aa85191 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/vrp87.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/vrp87.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-*"} } } */ +/* { dg-do compile { target { ! "m68k*-*-* mmix*-*-* mep*-*-* bfin*-*-* v850*-*-* picochip*-*-* moxie*-*-* cris*-*-* m32c*-*-* fr30*-*-* mcore*-*-* powerpc*-*-* xtensa*-*-* arc*-*-*"} } } */ /* { dg-options "-O2 -fdump-tree-vrp2-details -fdump-tree-cddce2-details" } */ /* { dg-additional-options "-mbranch-cost=2" { target avr-*-* } } */ |