Minor BRIG/HSAIL frontend updates and bug fixes:

* brig-builtins.def: Added a builtin for class_f64.
* builtin-types.def: Added a builtin type needed by class_f64.
* brigfrontend/brig-code-entry-handler.cc
 (brig_code_entry_handler::build_address_operand): Fix a bug
 with reg+offset addressing on 32b segments. In large mode,
 the offset is treated as 32bits unless it's global, readonly or
 kernarg address space.
* rt/workitems.c: Removed a leftover comment.
* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
 check for signaling/non-signalling NaN. Add class_f64 default
 implementation.

From-SVN: r247576

8 files changed, 75 insertions, 15 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6cf1215..8ab62c6 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-05-04  Pekka Jääskeläinen  <pekka.jaaskelainen@parmance.com>
+
+	* brig-builtins.def: Added a builtin for class_f64.
+	* builtin-types.def: Added a builtin type needed by class_f64.
+
 2017-05-03  Jason Merrill  <jason@redhat.com>
 
 	* timevar.def: Add TV_CONSTEXPR.
@@ -71,6 +76,7 @@
 	* ipa-inline.h (inline_summary): Add ctor.
 	(create_ggc): Do not use ggc_cleared_alloc.
 
+>>>>>>> .r247575
 2017-05-03  Jeff Downs  <heydowns@somuchpressure.net>
 	    Rainer Orth  <ro@CeBiTec.Uni-Bielefeld.DE>
 
diff --git a/gcc/brig-builtins.def b/gcc/brig-builtins.def
index b73ab7e..f525610 100644
--- a/gcc/brig-builtins.def
+++ b/gcc/brig-builtins.def
@@ -222,6 +222,10 @@ DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F32, BRIG_OPCODE_CLASS,
 		  BRIG_TYPE_F32, "__hsail_class_f32", BT_FN_UINT_FLOAT_UINT,
 		  ATTR_PURE_NOTHROW_LEAF_LIST)
 
+DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F64, BRIG_OPCODE_CLASS,
+		  BRIG_TYPE_F64, "__hsail_class_f64", BT_FN_UINT_DOUBLE_UINT,
+		  ATTR_PURE_NOTHROW_LEAF_LIST)
+
 DEF_HSAIL_BUILTIN (BUILT_IN_HSAIL_CLASS_F32_F16, BRIG_OPCODE_CLASS,
 		  BRIG_TYPE_F16, "__hsail_class_f32_f16", BT_FN_UINT_FLOAT_UINT,
 		  ATTR_PURE_NOTHROW_LEAF_LIST)
diff --git a/gcc/brig/ChangeLog b/gcc/brig/ChangeLog
index 9f9a27e..338873e 100644
--- a/gcc/brig/ChangeLog
+++ b/gcc/brig/ChangeLog
@@ -1,3 +1,11 @@
+2017-05-03  Pekka Jääskeläinen  <visit0r@kamu>
+
+	* brigfrontend/brig-code-entry-handler.cc
+	(brig_code_entry_handler::build_address_operand): Fix a bug
+	with reg+offset addressing on 32b segments. In large mode,
+	the offset is treated as 32bits unless it's global, readonly or
+	kernarg address space.
+
 2016-02-01  Pekka Jääskeläinen  <pekka.jaaskelainen@parmance.com>
 
 	* brigfrontend/brig-code-entry-handler.cc: fix address
diff --git a/gcc/brig/brigfrontend/brig-code-entry-handler.cc b/gcc/brig/brigfrontend/brig-code-entry-handler.cc
index 08e49f9..3abd80e 100644
--- a/gcc/brig/brigfrontend/brig-code-entry-handler.cc
+++ b/gcc/brig/brigfrontend/brig-code-entry-handler.cc
@@ -464,7 +464,24 @@ brig_code_entry_handler::build_address_operand
   uint64_t offs = gccbrig_to_uint64_t (addr_operand.offset);
   if (offs > 0 || addr == NULL_TREE)
     {
-      tree const_offset_2 = build_int_cst (size_type_node, offs);
+      /* In large mode, the offset is treated as 32bits unless it's
+	 global, readonly or kernarg address space.
+	 See:
+	 http://www.hsafoundation.com/html_spec111/HSA_Library.htm
+	 #PRM/Topics/02_ProgModel/small_and_large_machine_models.htm
+	 #table_machine_model_data_sizes */
+
+      int is64b_offset = segment == BRIG_SEGMENT_GLOBAL
+	|| segment == BRIG_SEGMENT_READONLY
+	|| segment == BRIG_SEGMENT_KERNARG;
+
+      /* The original offset is signed and should be sign
+	 extended for the pointer arithmetics.  */
+      tree const_offset_2 = is64b_offset
+        ? build_int_cst (size_type_node, offs)
+        : convert (long_integer_type_node,
+                   build_int_cst (integer_type_node, offs));
+
       if (addr == NULL_TREE)
 	addr = const_offset_2;
       else
@@ -1265,6 +1282,10 @@ brig_code_entry_handler::build_operands (const BrigInstBase &brig_inst)
 	  operand_type = uint32_type_node;
 	  half_to_float = false;
 	}
+      else if (brig_inst.opcode == BRIG_OPCODE_ACTIVELANEPERMUTE && i == 4)
+	{
+	  operand_type = uint32_type_node;
+	}
       else if (half_to_float)
 	/* Treat the operands as the storage type at this point.  */
 	operand_type = half_storage_type;
diff --git a/gcc/builtin-types.def b/gcc/builtin-types.def
index ac98944..2a51d25 100644
--- a/gcc/builtin-types.def
+++ b/gcc/builtin-types.def
@@ -348,6 +348,8 @@ DEF_FUNCTION_TYPE_2 (BT_FN_INT_INT_INT,
 		     BT_INT, BT_INT, BT_INT)
 DEF_FUNCTION_TYPE_2 (BT_FN_UINT_FLOAT_UINT,
 		     BT_UINT, BT_FLOAT, BT_UINT)
+DEF_FUNCTION_TYPE_2 (BT_FN_UINT_DOUBLE_UINT,
+		     BT_UINT, BT_DOUBLE, BT_UINT)
 DEF_FUNCTION_TYPE_2 (BT_FN_FLOAT_UINT_UINT,
 		     BT_FLOAT, BT_UINT, BT_UINT)
 DEF_FUNCTION_TYPE_2 (BT_FN_ULONG_UINT_UINT,
diff --git a/libhsail-rt/ChangeLog b/libhsail-rt/ChangeLog
index 70aecf3..31ffff6 100644
--- a/libhsail-rt/ChangeLog
+++ b/libhsail-rt/ChangeLog
@@ -1,3 +1,10 @@
+2017-05-03  Pekka Jääskeläinen  <pekka.jaaskelainen@parmance.com>
+
+	* rt/workitems.c: Removed a leftover comment.
+	* rt/arithmetic.c (__hsail_class_f32, __hsail_class_f64): Fix the
+	check for signaling/non-signalling NaN. Add class_f64 default
+	implementation.
+
 2017-02-01  Jakub Jelinek  <jakub@redhat.com>
 
 	* configure.tgt: Fix i?86-*-linux* entry.
diff --git a/libhsail-rt/rt/arithmetic.c b/libhsail-rt/rt/arithmetic.c
index 3d8e62c..80852d5 100644
--- a/libhsail-rt/rt/arithmetic.c
+++ b/libhsail-rt/rt/arithmetic.c
@@ -424,18 +424,34 @@ __hsail_fract_f64 (double a)
 uint32_t
 __hsail_class_f32 (float a, uint32_t flags)
 {
-  return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & 0x40000000))
-	 || (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & 0x40000000))
-	 || (flags & 0x0004 && isinf (a) && a < 0.0f)
-	 || (flags & 0x0008 && isnormal (a) && signbit (a))
-	 || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
-	 || (flags & 0x0020 && a == 0.0f && signbit (a))
-	 || (flags & 0x0040 && a == 0.0f && !signbit (a))
-	 || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
-	 || (flags & 0x0100 && isnormal (a) && !signbit (a))
-	 || (flags & 0x0200 && isinf (a) && a >= 0.0f);
+  return (flags & 0x0001 && isnan (a) && !(*(uint32_t *) &a & (1ul << 22)))
+    || (flags & 0x0002 && isnan (a) && (*(uint32_t *) &a & (1ul << 22)))
+    || (flags & 0x0004 && isinf (a) && a < 0.0f)
+    || (flags & 0x0008 && isnormal (a) && signbit (a))
+    || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
+    || (flags & 0x0020 && a == 0.0f && signbit (a))
+    || (flags & 0x0040 && a == 0.0f && !signbit (a))
+    || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
+    || (flags & 0x0100 && isnormal (a) && !signbit (a))
+    || (flags & 0x0200 && isinf (a) && a >= 0.0f);
 }
 
+uint32_t
+__hsail_class_f64 (double a, uint32_t flags)
+{
+  return (flags & 0x0001 && isnan (a) && !(*(uint64_t *) &a & (1ul << 51)))
+    || (flags & 0x0002 && isnan (a) && (*(uint64_t *) &a & (1ul << 51)))
+    || (flags & 0x0004 && isinf (a) && a < 0.0f)
+    || (flags & 0x0008 && isnormal (a) && signbit (a))
+    || (flags & 0x0010 && a < 0.0f && a > -FLT_MIN)
+    || (flags & 0x0020 && a == 0.0f && signbit (a))
+    || (flags & 0x0040 && a == 0.0f && !signbit (a))
+    || (flags & 0x0080 && a > 0.0f && a < FLT_MIN)
+    || (flags & 0x0100 && isnormal (a) && !signbit (a))
+    || (flags & 0x0200 && isinf (a) && a >= 0.0f);
+}
+
+
 /* 'class' for a f32-converted f16 which should otherwise be treated like f32
  except for its limits.  */
 
diff --git a/libhsail-rt/rt/workitems.c b/libhsail-rt/rt/workitems.c
index 1114e59..e2c2373 100644
--- a/libhsail-rt/rt/workitems.c
+++ b/libhsail-rt/rt/workitems.c
@@ -63,10 +63,6 @@ static clock_t start_time;
 #define FIBER_STACK_SIZE (64*1024)
 #define GROUP_SEGMENT_ALIGN 256
 
-/* HSA requires WGs to be executed in flat work-group id order.  Enabling
-   the following macro can reveal test cases that rely on the ordering,
-   but is not useful for much else.  */
-
 uint32_t __hsail_workitemabsid (uint32_t dim, PHSAWorkItem *context);
 
 uint32_t __hsail_workitemid (uint32_t dim, PHSAWorkItem *context);