diff options
| author | Uros Bizjak <ubizjak@gmail.com> | 2010-03-26 19:45:56 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2010-03-26 19:45:56 +0100 |
| commit | c5e43cc45b27e39016aa1dead023dc5edbd34eb2 (patch) | |
| tree | 407d2363cac73f350d0cefb2cf44c0dc1bb31d0a | |
| parent | fb04bb842fb8e5eb49f8066953da8e9064c24453 (diff) | |
| download | gcc-c5e43cc45b27e39016aa1dead023dc5edbd34eb2.zip gcc-c5e43cc45b27e39016aa1dead023dc5edbd34eb2.tar.gz gcc-c5e43cc45b27e39016aa1dead023dc5edbd34eb2.tar.bz2 | |
re PR target/42113 (Internal Compiler error with -O3, breaking commit known)
PR target/42113
* config/alpha/alpha.md (*cmp_sadd_si): Change mode
of scratch register to DImode. Split to DImode comparison operator.
Use SImode subreg of scratch register in the multiplication.
(*cmp_sadd_sidi): Ditto.
(*cmp_ssub_si): Ditto.
(*cmp_ssub_sidi): Ditto.
From-SVN: r157759
| -rw-r--r-- | gcc/ChangeLog | 10 | ||||
| -rw-r--r-- | gcc/config/alpha/alpha.md | 48 |
2 files changed, 38 insertions, 20 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index ffd5150..1dbd25b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,15 @@ 2010-03-26 Uros Bizjak <ubizjak@gmail.com> + PR target/42113 + * config/alpha/alpha.md (*cmp_sadd_si): Change mode + of scratch register to DImode. Split to DImode comparison operator. + Use SImode subreg of scratch register in the multiplication. + (*cmp_sadd_sidi): Ditto. + (*cmp_ssub_si): Ditto. + (*cmp_ssub_sidi): Ditto. + +2010-03-26 Uros Bizjak <ubizjak@gmail.com> + PR target/43524 * config/i386/i386.c (ix86_expand_prologue) [TARGET_STACK_PROBE]: Remove invalid assert and wrong comment. diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md index 6a1c43a..e5f8c12 100644 --- a/gcc/config/alpha/alpha.md +++ b/gcc/config/alpha/alpha.md @@ -4186,20 +4186,22 @@ (match_operand:SI 3 "const48_operand" "I") (const_int 0)) (match_operand:SI 4 "sext_add_operand" "rIO"))) - (clobber (match_scratch:SI 5 "=r"))] + (clobber (match_scratch:DI 5 "=r"))] "" "#" "" [(set (match_dup 5) - (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) + (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) - (plus:SI (mult:SI (match_dup 5) (match_dup 3)) + (plus:SI (mult:SI (match_dup 6) (match_dup 3)) (match_dup 4)))] { if (can_create_pseudo_p ()) - operands[5] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (DImode); else if (reg_overlap_mentioned_p (operands[5], operands[4])) - operands[5] = operands[0]; + operands[5] = gen_lowpart (DImode, operands[0]); + + operands[6] = gen_lowpart (SImode, operands[5]); }) (define_insn_and_split "*cmp_sadd_sidi" @@ -4212,20 +4214,22 @@ (match_operand:SI 3 "const48_operand" "I") (const_int 0)) (match_operand:SI 4 "sext_add_operand" "rIO")))) - (clobber (match_scratch:SI 5 "=r"))] + (clobber (match_scratch:DI 5 "=r"))] "" "#" "" [(set (match_dup 5) - (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) + (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) - (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3)) + (sign_extend:DI (plus:SI (mult:SI (match_dup 6) (match_dup 3)) (match_dup 4))))] { if (can_create_pseudo_p ()) - operands[5] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (DImode); else if (reg_overlap_mentioned_p (operands[5], operands[4])) - operands[5] = gen_lowpart (SImode, operands[0]); + operands[5] = operands[0]; + + operands[6] = gen_lowpart (SImode, operands[5]); }) (define_insn_and_split "*cmp_ssub_di" @@ -4262,20 +4266,22 @@ (match_operand:SI 3 "const48_operand" "I") (const_int 0)) (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) - (clobber (match_scratch:SI 5 "=r"))] + (clobber (match_scratch:DI 5 "=r"))] "" "#" "" [(set (match_dup 5) - (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) + (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) - (minus:SI (mult:SI (match_dup 5) (match_dup 3)) + (minus:SI (mult:SI (match_dup 6) (match_dup 3)) (match_dup 4)))] { if (can_create_pseudo_p ()) - operands[5] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (DImode); else if (reg_overlap_mentioned_p (operands[5], operands[4])) - operands[5] = operands[0]; + operands[5] = gen_lowpart (DImode, operands[0]); + + operands[6] = gen_lowpart (SImode, operands[5]); }) (define_insn_and_split "*cmp_ssub_sidi" @@ -4288,20 +4294,22 @@ (match_operand:SI 3 "const48_operand" "I") (const_int 0)) (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) - (clobber (match_scratch:SI 5 "=r"))] + (clobber (match_scratch:DI 5 "=r"))] "" "#" "" [(set (match_dup 5) - (match_op_dup:SI 1 [(match_dup 2) (const_int 0)])) + (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) (set (match_dup 0) - (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3)) + (sign_extend:DI (minus:SI (mult:SI (match_dup 6) (match_dup 3)) (match_dup 4))))] { if (can_create_pseudo_p ()) - operands[5] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (DImode); else if (reg_overlap_mentioned_p (operands[5], operands[4])) - operands[5] = gen_lowpart (SImode, operands[0]); + operands[5] = operands[0]; + + operands[6] = gen_lowpart (SImode, operands[5]); }) ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF |