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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-04-23 19:33:54 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-04-24 14:18:29 +0800 |
| commit | c5a1fa59ae3f44059a79086cbc506800d4149b69 (patch) | |
| tree | d41ef86fb9c678a3b72dc4348a3b3db73fda940c | |
| parent | 4eae76d10433b12bdb6944c2b3be818ccc3b5986 (diff) | |
| download | gcc-c5a1fa59ae3f44059a79086cbc506800d4149b69.zip gcc-c5a1fa59ae3f44059a79086cbc506800d4149b69.tar.gz gcc-c5a1fa59ae3f44059a79086cbc506800d4149b69.tar.bz2 | |
RISC-V: Add function comment for cleanup_insns.
Add more comment for cleanup_insns.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::pre_vsetvl): Add function
comment for cleanup_insns.
| -rw-r--r-- | gcc/config/riscv/riscv-vsetvl.cc | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc index ac99028..fa68b8a 100644 --- a/gcc/config/riscv/riscv-vsetvl.cc +++ b/gcc/config/riscv/riscv-vsetvl.cc @@ -3998,6 +3998,21 @@ pass_vsetvl::pre_vsetvl (void) commit_edge_insertions (); } +/* Before VSETVL PASS, RVV instructions pattern is depending on AVL operand + implicitly. Since we will emit VSETVL instruction and make RVV instructions + depending on VL/VTYPE global status registers, we remove the such AVL operand + in the RVV instructions pattern here in order to remove AVL dependencies when + AVL operand is a register operand. + + Before the VSETVL PASS: + li a5,32 + ... + vadd.vv (..., a5) + After the VSETVL PASS: + li a5,32 + vsetvli zero, a5, ... + ... + vadd.vv (..., const_int 0). */ void pass_vsetvl::cleanup_insns (void) const { |