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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-13 15:09:46 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2023-03-15 09:56:25 +0100 |
| commit | c36fb3ca9eef56bc2f597e0fee577aca96ec3754 (patch) | |
| tree | b9a76f59fbf74ea93e8a39463173748152330919 | |
| parent | 8351535f20b52cf332791f60d2bf22a025833516 (diff) | |
| download | gcc-c36fb3ca9eef56bc2f597e0fee577aca96ec3754.zip gcc-c36fb3ca9eef56bc2f597e0fee577aca96ec3754.tar.gz gcc-c36fb3ca9eef56bc2f597e0fee577aca96ec3754.tar.bz2 | |
riscv: riscv-cores.def: Add T-Head XuanTie C906
This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906".
The C906 is shipped for quite some time (it is the core of the Allwinner D1).
Note, that the tuning struct for the C906 is already part of GCC (it is
also name "thead-c906").
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906".
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-thead-c906.c: New test.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | gcc/config/riscv/riscv-cores.def | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c | 28 |
2 files changed, 32 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 2a834ca..7d87ab7 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -73,4 +73,8 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" + "xtheadcondmov_xtheadfmemidx_xtheadmac_" + "xtheadmemidx_xtheadmempair_xtheadsync", + "thead-c906") #undef RISCV_CORE diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c new file mode 100644 index 0000000..a71b43a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */ +/* T-Head XuanTie C906 => rv64imafdc */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed) \ + && defined(__riscv_xtheadba) \ + && defined(__riscv_xtheadbb) \ + && defined(__riscv_xtheadbs) \ + && defined(__riscv_xtheadcmo) \ + && defined(__riscv_xtheadcondmov) \ + && defined(__riscv_xtheadfmemidx) \ + && defined(__riscv_xtheadmac) \ + && defined(__riscv_xtheadmemidx) \ + && defined(__riscv_xtheadmempair) \ + && defined(__riscv_xtheadsync)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} |