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| author | David Edelsohn <edelsohn@mhpcc.edu> | 1998-09-03 15:12:09 +0000 |
|---|---|---|
| committer | David Edelsohn <dje@gcc.gnu.org> | 1998-09-03 11:12:09 -0400 |
| commit | c29b0711461ddf53f2cb0c61f802ccd198ea3b0d (patch) | |
| tree | 022330cdcbe616fd420cb1efb6abf8b5f969d59e | |
| parent | d6c6ba304d55824283b213de69a8e18666e2dae4 (diff) | |
| download | gcc-c29b0711461ddf53f2cb0c61f802ccd198ea3b0d.zip gcc-c29b0711461ddf53f2cb0c61f802ccd198ea3b0d.tar.gz gcc-c29b0711461ddf53f2cb0c61f802ccd198ea3b0d.tar.bz2 | |
rs6000.md (movsf): Disable explicit secondary-reload-like functionality if TARGET_POWERPC64.
* rs6000.md (movsf): Disable explicit secondary-reload-like
functionality if TARGET_POWERPC64.
(movdf): Remove TARGET_POWERPC64 explicit secondary-reload-like
functionality.
From-SVN: r22213
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/rs6000/rs6000.md | 23 |
2 files changed, 11 insertions, 19 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0d89f27..77aaa27 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +Thu Sep 3 18:05:16 1998 David Edelsohn <edelsohn@mhpcc.edu> + + * rs6000.md (movsf): Disable explicit secondary-reload-like + functionality if TARGET_POWERPC64. + (movdf): Remove TARGET_POWERPC64 explicit secondary-reload-like + functionality. + Thu Sep 3 11:41:40 1998 Robert Lipe <robertl@dgii.com> * fixinc.sco: Borrow code to wrap 'bool' typedefs from tinfo.h diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 65af962..2306407 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5686,7 +5686,8 @@ else if (TARGET_HARD_FLOAT) { - if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) + if (! TARGET_POWERPC64 + && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32) { /* If this is a store to memory or another integer register do the move directly. Otherwise store to a temporary stack slot and @@ -5729,7 +5730,8 @@ operands[1] = force_reg (SFmode, operands[1]); } - if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) + if (! TARGET_POWERPC64 + && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32) { if (GET_CODE (operands[1]) == MEM #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE) @@ -5848,23 +5850,6 @@ if (GET_CODE (operands[0]) != REG) operands[1] = force_reg (DFmode, operands[1]); - /* Stores between FPR and any non-FPR registers must go through a - temporary stack slot. */ - - if (TARGET_POWERPC64 - && GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG - && ((FP_REGNO_P (REGNO (operands[0])) - && ! FP_REGNO_P (REGNO (operands[1]))) - || (FP_REGNO_P (REGNO (operands[1])) - && ! FP_REGNO_P (REGNO (operands[0]))))) - { - rtx stack_slot = assign_stack_temp (DFmode, 8, 0); - - emit_move_insn (stack_slot, operands[1]); - emit_move_insn (operands[0], stack_slot); - DONE; - } - if (CONSTANT_P (operands[1]) && ! easy_fp_constant (operands[1], DFmode)) { operands[1] = force_const_mem (DFmode, operands[1]); |