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| author | Uros Bizjak <ubizjak@gmail.com> | 2021-05-23 22:14:21 +0200 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2021-05-23 22:14:59 +0200 |
| commit | c01c4331112aaf45f0de20ed8883dbeab83ed896 (patch) | |
| tree | 666fb1a08c3b7ae0fbb931a42160581a9f2afa73 | |
| parent | fe03f4fc9548b3fdbff3c8284a994feaa7d6307d (diff) | |
| download | gcc-c01c4331112aaf45f0de20ed8883dbeab83ed896.zip gcc-c01c4331112aaf45f0de20ed8883dbeab83ed896.tar.gz gcc-c01c4331112aaf45f0de20ed8883dbeab83ed896.tar.bz2 | |
i386: Add push insns for 4-byte vectors [PR100722]
2021-05-23 Uroš Bizjak <ubizjak@gmail.com>
gcc/
PR target/100722
* config/i386/mmx.md (*push<VI_32:mode>2_rex64):
New instruction pattern.
(*push<VI_32:mode>2): Ditto.
(push splitter for SSE registers): New splitter.
gcc/testsuite/
PR target/100722
* gcc.target/i386/pr100722.c: New test.
| -rw-r--r-- | gcc/config/i386/mmx.md | 33 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr100722.c | 17 |
2 files changed, 50 insertions, 0 deletions
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 4c42e6d..453e8ea 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -302,6 +302,39 @@ ] (symbol_ref "true")))]) +;; For TARGET_64BIT we always round up to 8 bytes. +(define_insn "*push<mode>2_rex64" + [(set (match_operand:VI_32 0 "push_operand" "=X,X") + (match_operand:VI_32 1 "nonmemory_no_elim_operand" "rC,*v"))] + "TARGET_SSE2 && TARGET_64BIT" + "@ + push{q}\t%q1 + #" + [(set_attr "type" "push,multi") + (set_attr "mode" "DI")]) + +(define_insn "*push<mode>2" + [(set (match_operand:VI_32 0 "push_operand" "=<,<") + (match_operand:VI_32 1 "general_no_elim_operand" "rC*m,*v"))] + "TARGET_SSE2 && !TARGET_64BIT" + "@ + push{l}\t%1 + #" + [(set_attr "type" "push,multi") + (set_attr "mode" "SI")]) + +(define_split + [(set (match_operand:VI_32 0 "push_operand") + (match_operand:VI_32 1 "sse_reg_operand"))] + "TARGET_SSE2 && reload_completed" + [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2))) + (set (match_dup 0) (match_dup 1))] +{ + operands[2] = GEN_INT (-PUSH_ROUNDING (GET_MODE_SIZE (<VI_32:MODE>mode))); + /* Preserve memory attributes. */ + operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx); +}) + (define_expand "movmisalign<mode>" [(set (match_operand:VI_32 0 "nonimmediate_operand") (match_operand:VI_32 1 "nonimmediate_operand"))] diff --git a/gcc/testsuite/gcc.target/i386/pr100722.c b/gcc/testsuite/gcc.target/i386/pr100722.c new file mode 100644 index 0000000..f784039 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr100722.c @@ -0,0 +1,17 @@ +/* PR target/100722 */ +/* { dg-do compile } */ +/* { dg-options "-O -msse2" } */ + +typedef char int8x4_t __attribute__((vector_size(4))); + +void stack_callee (int8x4_t, int8x4_t, int8x4_t, int8x4_t, + int8x4_t, int8x4_t, int8x4_t); + +int8x4_t stack_caller_x1; + +void stack_caller (void) +{ + stack_callee (stack_caller_x1, stack_caller_x1, stack_caller_x1, + stack_caller_x1, stack_caller_x1, stack_caller_x1, + stack_caller_x1); +} |