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| author | Jakub Jelinek <jakub@redhat.com> | 2023-12-05 09:08:45 +0100 |
|---|---|---|
| committer | Jakub Jelinek <jakub@redhat.com> | 2023-12-05 09:08:45 +0100 |
| commit | bf418db27c0b48abb8203dd9e08135793cd9ce18 (patch) | |
| tree | 0b0025ed6796575cb26edae8f22b868c35674ddf | |
| parent | 8b93a0f3eb46cbc4ba8eece8eba58aaade4399b6 (diff) | |
| download | gcc-bf418db27c0b48abb8203dd9e08135793cd9ce18.zip gcc-bf418db27c0b48abb8203dd9e08135793cd9ce18.tar.gz gcc-bf418db27c0b48abb8203dd9e08135793cd9ce18.tar.bz2 | |
i386: Improve code generation for vector __builtin_signbit (x.x[i]) ? -1 : 0 [PR112816]
On the testcase I've recently fixed I've noticed bad code generation,
we emit
pxor %xmm1, %xmm1
psrld $31, %xmm0
pcmpeqd %xmm1, %xmm0
pcmpeqd %xmm1, %xmm0
or
vpxor %xmm1, %xmm1, %xmm1
vpsrld $31, %xmm0, %xmm0
vpcmpeqd %xmm1, %xmm0, %xmm0
vpcmpeqd %xmm1, %xmm0, %xmm2
rather than
psrad $31, %xmm2
or
vpsrad $31, %xmm1, %xmm2
The following patch fixes that using a combiner splitter.
2023-12-05 Jakub Jelinek <jakub@redhat.com>
PR target/112816
* config/i386/sse.md ((eq (eq (lshiftrt x elt_bits-1) 0) 0)): New
splitter to turn psrld $31; pcmpeq; pcmpeq into psrad $31.
* gcc.target/i386/pr112816.c: New test.
| -rw-r--r-- | gcc/config/i386/sse.md | 12 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr112816.c | 27 |
2 files changed, 39 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 4c81f66..edd6f66 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16614,6 +16614,18 @@ DONE; }) +(define_split + [(set (match_operand:VI248_AVX2 0 "register_operand") + (eq:VI248_AVX2 + (eq:VI248_AVX2 + (lshiftrt:VI248_AVX2 + (match_operand:VI248_AVX2 1 "register_operand") + (match_operand:SI 2 "const_int_operand")) + (match_operand:VI248_AVX2 3 "const0_operand")) + (match_operand:VI248_AVX2 4 "const0_operand")))] + "INTVAL (operands[2]) == GET_MODE_PRECISION (<ssescalarmode>mode) - 1" + [(set (match_dup 0) (ashiftrt:VI248_AVX2 (match_dup 1) (match_dup 2)))]) + (define_expand "rotlv1ti3" [(set (match_operand:V1TI 0 "register_operand") (rotate:V1TI diff --git a/gcc/testsuite/gcc.target/i386/pr112816.c b/gcc/testsuite/gcc.target/i386/pr112816.c new file mode 100644 index 0000000..4748156 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr112816.c @@ -0,0 +1,27 @@ +/* PR target/112816 */ +/* { dg-do compile } */ +/* { dg-options "-O2 -mno-avx512f -masm=att" } */ +/* { dg-final { scan-assembler-times "psrad\t\\\$31," 2 } } */ +/* { dg-final { scan-assembler-not "pcmpeqd\t" } } */ + +#define N 4 +struct S { float x[N]; }; +struct T { int x[N]; }; + +__attribute__((target ("no-sse3,sse2"))) struct T +foo (struct S x) +{ + struct T res; + for (int i = 0; i < N; ++i) + res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0; + return res; +} + +__attribute__((target ("avx2"))) struct T +bar (struct S x) +{ + struct T res; + for (int i = 0; i < N; ++i) + res.x[i] = __builtin_signbit (x.x[i]) ? -1 : 0; + return res; +} |