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| author | Matthieu Longo <matthieu.longo@arm.com> | 2024-01-29 15:54:35 +0000 |
|---|---|---|
| committer | Richard Earnshaw <rearnsha@arm.com> | 2024-01-29 15:54:35 +0000 |
| commit | bad991a1c5960e90c4686a9362a1258ef29e195b (patch) | |
| tree | d58e685022253266bb41aa0d61a5fc27efbb5987 | |
| parent | 0f7945417f913c85bd556904c0c4e7bf77793488 (diff) | |
| download | gcc-bad991a1c5960e90c4686a9362a1258ef29e195b.zip gcc-bad991a1c5960e90c4686a9362a1258ef29e195b.tar.gz gcc-bad991a1c5960e90c4686a9362a1258ef29e195b.tar.bz2 | |
arm: Add pattern for bswap + rotate -> rev16 [Bug 108933]
The rev16 pattern was not recognised anymore as a change in the bswap
tree pass was introducing a new GIMPLE form, not recognized by the
assembly final transformation pass.
Also, fix the output patterns for arm_rev16si_alt[12] to correctly
handle the instructions being made conditional.
More details in the PR.
gcc/ChangeLog:
PR target/108933
* config/arm/arm.md (arm_rev16si2): Convert to define_insn.
Correct generated RTL.
(arm_rev16si2_alt1): Correctly handle conditional execution.
(arm_rev16si2_alt2): Likewise.
gcc/testsuite/ChangeLog:
PR target/108933
* gcc.target/arm/rev16.c: Moved to...
* gcc.target/arm/rev16_1.c: ...here.
* gcc.target/arm/rev16_2.c: New test to check that rev16 is emitted.
| -rw-r--r-- | gcc/config/arm/arm.md | 31 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/rev16_1.c (renamed from gcc/testsuite/gcc.target/arm/rev16.c) | 0 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arm/rev16_2.c | 20 |
3 files changed, 40 insertions, 11 deletions
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 4a98f2d..5816409 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12578,7 +12578,10 @@ "arm_arch6 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" - "rev16\\t%0, %1" + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "type" "rev")] @@ -12595,22 +12598,28 @@ "arm_arch6 && aarch_rev16_shleft_mask_imm_p (operands[3], SImode) && aarch_rev16_shright_mask_imm_p (operands[2], SImode)" - "rev16\\t%0, %1" + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" [(set_attr "arch" "t1,t2,32") (set_attr "length" "2,2,4") (set_attr "type" "rev")] ) -(define_expand "arm_rev16si2" - [(set (match_operand:SI 0 "s_register_operand") - (bswap:SI (match_operand:SI 1 "s_register_operand")))] +;; Similar pattern to match (rotate (bswap) 16) +(define_insn "arm_rev16si2" + [(set (match_operand:SI 0 "register_operand" "=l,l,r") + (rotate:SI (bswap:SI (match_operand:SI 1 "register_operand" "l,l,r")) + (const_int 16)))] "arm_arch6" - { - rtx left = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff00), SImode); - rtx right = gen_int_mode (HOST_WIDE_INT_C (0xff00ff00ff00ff), SImode); - emit_insn (gen_arm_rev16si2_alt1 (operands[0], operands[1], right, left)); - DONE; - } + "@ + rev16\t%0, %1 + rev16%?\t%0, %1 + rev16%?\t%0, %1" + [(set_attr "arch" "t1,t2,32") + (set_attr "length" "2,2,4") + (set_attr "type" "rev")] ) (define_expand "bswaphi2" diff --git a/gcc/testsuite/gcc.target/arm/rev16.c b/gcc/testsuite/gcc.target/arm/rev16_1.c index 1c869b3..1c869b3 100644 --- a/gcc/testsuite/gcc.target/arm/rev16.c +++ b/gcc/testsuite/gcc.target/arm/rev16_1.c diff --git a/gcc/testsuite/gcc.target/arm/rev16_2.c b/gcc/testsuite/gcc.target/arm/rev16_2.c new file mode 100644 index 0000000..c6553b3 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/rev16_2.c @@ -0,0 +1,20 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +/* { dg-final { scan-assembler-times {rev16\tr[0-9]+, r[0-9]+} 2 } } */ |