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| author | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-09 13:43:14 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2021-04-09 13:43:14 +0100 |
| commit | ba2913f618ab2fecf15355f936028a39b5a9db87 (patch) | |
| tree | 4b67b0eb8f9cfdbaa0333ca0fe5b347fb6dc9b69 | |
| parent | 40ccb47b505b528244ee305923681c0ae3b6f4d5 (diff) | |
| download | gcc-ba2913f618ab2fecf15355f936028a39b5a9db87.zip gcc-ba2913f618ab2fecf15355f936028a39b5a9db87.tar.gz gcc-ba2913f618ab2fecf15355f936028a39b5a9db87.tar.bz2 | |
aarch64: Use x30 as temporary in SVE TLSDESC patterns
gcc.dg/torture/tls/tls-reload-1.c started ICEing for SVE some time
during the GCC 11 cycle (not sure when). The problem is that we
had an output reload on a call_insn, which isn't a supported
combination.
This patch uses LR_REGNUM instead. The resulting "blr x30"
might not perform as well on some CPUs, but in this context
the difference shouldn't be noticeable.
gcc/
* config/aarch64/aarch64.md (tlsdesc_small_sve_<mode>): Use X30
as the temporary register.
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 15bbc10..a149748 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -6818,10 +6818,9 @@ UNSPEC_TLSDESC)) (const_int 0))) (unspec:DI [(match_operand:DI 1 "const_int_operand")] UNSPEC_CALLEE_ABI) - (clobber (reg:DI LR_REGNUM)) - (clobber (match_scratch:DI 2 "=r"))] + (clobber (reg:DI LR_REGNUM))] "TARGET_TLS_DESC && TARGET_SVE" - "adrp\\tx0, %A0\;ldr\\t%<w>2, [x0, #%L0]\;add\\t<w>0, <w>0, %L0\;.tlsdesccall\\t%0\;blr\\t%2" + "adrp\\tx0, %A0\;ldr\\t<w>30, [x0, #%L0]\;add\\t<w>0, <w>0, %L0\;.tlsdesccall\\t%0\;blr\\tx30" [(set_attr "type" "call") (set_attr "length" "16")]) |