Added RISC-V target hook (or at least provisional one)

5 files changed, 73 insertions, 0 deletions

diff --git a/gcc/config.gcc b/gcc/config.gcc
index 6a006ef..a3a1995 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -558,6 +558,7 @@ riscv*)
 	cpu_type=riscv
 	extra_objs="riscv-builtins.o riscv-c.o riscv-sr.o riscv-shorten-memrefs.o"
 	d_target_objs="riscv-d.o"
+	rust_target_objs="riscv-rust.o"
 	;;
 rs6000*-*-*)
 	extra_options="${extra_options} g.opt fused-madd.opt rs6000/rs6000-tables.opt"
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
index 256dab1..3b5cf7a 100644
--- a/gcc/config/riscv/riscv-protos.h
+++ b/gcc/config/riscv/riscv-protos.h
@@ -81,6 +81,9 @@ void riscv_cpu_cpp_builtins (cpp_reader *);
 /* Routines implemented in riscv-d.c  */
 extern void riscv_d_target_versions (void);
 
+/* Routines implemented in riscv-rust.c  */
+extern void riscv_rust_target_cpu_info (void);
+
 /* Routines implemented in riscv-builtins.c.  */
 extern void riscv_atomic_assign_expand_fenv (tree *, tree *, tree *);
 extern rtx riscv_expand_builtin (tree, rtx, rtx, machine_mode, int);
diff --git a/gcc/config/riscv/riscv-rust.c b/gcc/config/riscv/riscv-rust.c
new file mode 100644
index 0000000..f60a6ef
--- /dev/null
+++ b/gcc/config/riscv/riscv-rust.c
@@ -0,0 +1,60 @@
+/* Subroutines for the Rust front end for the RISC-V architecture.
+   Copyright (C) 2020 Free Software Foundation, Inc.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+#include "config.h"
+#include "system.h"
+#include "coretypes.h"
+#include "tm.h"
+#include "tm_p.h"
+#include "rust/rust-target.h"
+#include "rust/rust-target-def.h"
+
+/* Implement TARGET_RUST_CPU_INFO for RISC-V targets.  */
+
+void riscv_rust_target_cpu_info(void) {
+    if (TARGET_64BIT)
+        rust_add_target_info("target_arch", "riscv64");
+    else
+        rust_add_target_info("target_arch", "riscv32");
+
+    // names derived from rustc and llvm 
+    if (TARGET_SAVE_RESTORE) 
+        rust_add_target_info("target_feature", "save-restore");
+    // TODO: ensure below variable works
+    if (riscv_mrelax)
+        rust_add_target_info("target_feature", "relax");
+    if (TARGET_MUL)
+        rust_add_target_info("target_feature", "m");
+    if (TARGET_ATOMIC)
+        rust_add_target_info("target_feature", "a");
+    if (TARGET_HARD_FLOAT)
+        rust_add_target_info("target_feature", "f");
+    if (TARGET_DOUBLE_FLOAT)
+        rust_add_target_info("target_feature", "d");
+    if (TARGET_RVC)
+        rust_add_target_info("target_feature", "c");
+    if (TARGET_RVE)
+        rust_add_target_info("target_feature", "e");
+    // TODO: add features based on "B" and "V" extensions when gcc adds them
+    // TODO: if gcc has it, add "no-rvc-hints" flag 
+    // TODO: if gcc has it, add reserve-x1 -> reserve-x31 (user reserve registers)
+    if (TARGET_64BIT)
+        rust_add_target_info("target_feature", "64bit");
+    /* TODO: maybe add gcc features with no llvm equivalent, e.g. align-data, riscv-attribute, 
+     * explicit-relocs, strict-align, cmodel, small-data-limit, branch-cost, plt, abi, 
+     * preferred-stack-boundary, fdiv, div */
+}
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index e71fbf3..8b6ea7b 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -30,6 +30,9 @@ along with GCC; see the file COPYING3.  If not see
 /* Target CPU versions for D.  */
 #define TARGET_D_CPU_VERSIONS riscv_d_target_versions
 
+/* Target CPU info for Rust.  */
+#define TARGET_RUST_CPU_INFO riscv_rust_target_cpu_info
+
 /* Default target_flags if no switches are specified  */
 
 #ifndef TARGET_DEFAULT
diff --git a/gcc/config/riscv/t-riscv b/gcc/config/riscv/t-riscv
index 702767c..b1acb07 100644
--- a/gcc/config/riscv/t-riscv
+++ b/gcc/config/riscv/t-riscv
@@ -19,6 +19,7 @@ riscv-d.o: $(srcdir)/config/riscv/riscv-d.c
 	$(COMPILE) $<
 	$(POSTCOMPILE)
 
+
 riscv-shorten-memrefs.o: $(srcdir)/config/riscv/riscv-shorten-memrefs.c
 	$(COMPILE) $<
 	$(POSTCOMPILE)
@@ -26,3 +27,8 @@ riscv-shorten-memrefs.o: $(srcdir)/config/riscv/riscv-shorten-memrefs.c
 PASSES_EXTRA += $(srcdir)/config/riscv/riscv-passes.def
 
 $(common_out_file): $(srcdir)/config/riscv/riscv-cores.def
+
+riscv-rust.o: $(srcdir)/config/riscv/riscv-rust.c \
+  $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) $(TREE_H) $(C_COMMON_H)
+	$(COMPILER) -c $(ALL_COMPILERFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $<
+