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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-05-31 18:43:44 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-05-31 21:52:46 +0800 |
| commit | b65458005dfb38f2efdca52e42f3dbf4760f91bd (patch) | |
| tree | ab9739359f60b1ebe9308494a6302132187607e1 | |
| parent | e2a326227977dd361bb3b52b8409ebc57240a2a7 (diff) | |
| download | gcc-b65458005dfb38f2efdca52e42f3dbf4760f91bd.zip gcc-b65458005dfb38f2efdca52e42f3dbf4760f91bd.tar.gz gcc-b65458005dfb38f2efdca52e42f3dbf4760f91bd.tar.bz2 | |
RISC-V: Remove FRM for vfwcvt.f.x<u>.v (RVV integer to float widening conversion)
Base on the discussion here:
https://github.com/riscv/riscv-v-spec/issues/884
vfwcvt.f.x<u>.v doesn't depend on FRM. So remove FRM preparing for mode switching support.
gcc/ChangeLog:
* config/riscv/vector.md: Remove FRM.
Signed-off-by: Pan Li <pan2.li@intel.com>
| -rw-r--r-- | gcc/config/riscv/vector.md | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 60f052b..cb4e77e 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7159,10 +7159,8 @@ (match_operand 5 "const_int_operand" " i, i") (match_operand 6 "const_int_operand" " i, i") (match_operand 7 "const_int_operand" " i, i") - (match_operand 8 "const_int_operand" " i, i") (reg:SI VL_REGNUM) - (reg:SI VTYPE_REGNUM) - (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) + (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (any_float:VF (match_operand:<VNCONVERT> 3 "register_operand" " vr, vr")) (match_operand:VF 2 "vector_merge_operand" " vu, 0")))] |