RISC-V: delete all the vector psabi checking.

Thanks the
https://hub.fgit.cf/riscv-non-isa/riscv-elf-psabi-doc/pull/389, we
need not to maintain the psabi checking any more.

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
	(riscv_pass_in_vector_p): Delete.
	(riscv_init_cumulative_args): Delete the checking.
	(riscv_get_arg_info): Delete the checking.
	(riscv_function_value): Delete the checking.
	* config/riscv/riscv.h: Delete the member for checking.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/binop_vx_constraint-120.c: Delete the -Wno-psabi.
	* gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c: Ditto.
	* gcc.target/riscv/rvv/base/mask_insn_shortcut.c: Ditto.
	* gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto.
	* gcc.target/riscv/rvv/base/pr110109-2.c: Ditto.
	* gcc.target/riscv/rvv/base/scalar_move-9.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-10.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-11.c: Ditto.
	* gcc.target/riscv/rvv/base/spill-9.c: Ditto.
	* gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto.
	* gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c: Ditto.
	* gcc.target/riscv/rvv/base/zvfh-intrinsic.c: Ditto.
	* gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto.
	* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: Ditto.
	* gcc.target/riscv/rvv/base/vector-abi-1.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-2.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-3.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-4.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-5.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-6.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-7.c: Removed.
	* gcc.target/riscv/rvv/base/vector-abi-8.c: Removed.

Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com>
Signed-off-by: Yanzhang Wang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>

24 files changed, 15 insertions, 222 deletions

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 568db90..89caf15 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4865,59 +4865,6 @@ riscv_pass_fpr_pair (machine_mode mode, unsigned regno1,
 				   GEN_INT (offset2))));
 }
 
-/* Return true if a vector type is included in the type TYPE.  */
-
-static bool
-riscv_arg_has_vector (const_tree type)
-{
-  if (riscv_v_ext_mode_p (TYPE_MODE (type)))
-    return true;
-
-  if (!COMPLETE_TYPE_P (type))
-    return false;
-
-  switch (TREE_CODE (type))
-    {
-    case RECORD_TYPE:
-      /* If it is a record, it is further determined whether its fields have
-	 vector type.  */
-      for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f))
-	if (TREE_CODE (f) == FIELD_DECL)
-	  {
-	    tree field_type = TREE_TYPE (f);
-	    if (!TYPE_P (field_type))
-	      break;
-
-	    if (riscv_arg_has_vector (field_type))
-	      return true;
-	  }
-      break;
-    case ARRAY_TYPE:
-      return riscv_arg_has_vector (TREE_TYPE (type));
-    default:
-      break;
-    }
-
-  return false;
-}
-
-/* Pass the type to check whether it's a vector type or contains vector type.
-   Only check the value type and no checking for vector pointer type.  */
-
-static void
-riscv_pass_in_vector_p (const_tree type)
-{
-  static int warned = 0;
-
-  if (type && riscv_vector::lookup_vector_type_attribute (type) && !warned)
-    {
-      warning (OPT_Wpsabi,
-	       "ABI for the vector type is currently in experimental stage and "
-	       "may changes in the upcoming version of GCC.");
-      warned = 1;
-    }
-}
-
 /* Initialize a variable CUM of type CUMULATIVE_ARGS
    for a call to a function whose data type is FNTYPE.
    For a library call, FNTYPE is 0.  */
@@ -4935,15 +4882,6 @@ riscv_init_cumulative_args (CUMULATIVE_ARGS *cum,
     cum->variant_cc = (riscv_cc) fntype_abi (fntype).id ();
   else
     cum->variant_cc = RISCV_CC_BASE;
-
-  if (fndecl)
-    {
-      const tree_function_decl &fn
-	= FUNCTION_DECL_CHECK (fndecl)->function_decl;
-
-      if (fn.built_in_class == NOT_BUILT_IN)
-	  cum->rvv_psabi_warning = 1;
-    }
 }
 
 /* Return true if TYPE is a vector type that can be passed in vector registers.
@@ -5060,12 +4998,6 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum,
   info->gpr_offset = cum->num_gprs;
   info->fpr_offset = cum->num_fprs;
 
-  if (cum->rvv_psabi_warning)
-    {
-      /* Only check existing of vector type.  */
-      riscv_pass_in_vector_p (type);
-    }
-
   /* When disable vector_abi or scalable vector argument is anonymous, this
      argument is passed by reference.  */
   if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named))
@@ -5243,17 +5175,7 @@ riscv_function_value (const_tree type, const_tree func, machine_mode mode)
 
   memset (&args, 0, sizeof args);
 
-  const_tree arg_type = type;
-  if (func && DECL_RESULT (func))
-    {
-      const tree_function_decl &fn = FUNCTION_DECL_CHECK (func)->function_decl;
-      if (fn.built_in_class == NOT_BUILT_IN)
-	args.rvv_psabi_warning = 1;
-
-      arg_type = TREE_TYPE (DECL_RESULT (func));
-    }
-
-  return riscv_get_arg_info (&info, &args, mode, arg_type, true, true);
+  return riscv_get_arg_info (&info, &args, mode, type, true, true);
 }
 
 /* Implement TARGET_PASS_BY_REFERENCE. */
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index 15d554e..1b2cb8d 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -736,8 +736,6 @@ typedef struct {
   /* Number of floating-point registers used so far, likewise.  */
   unsigned int num_fprs;
 
-  int rvv_psabi_warning;
-
   /* Number of mask registers used so far, up to MAX_ARGS_IN_MASK_REGISTERS.  */
   unsigned int num_mrs;
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
index cc37346..809b185 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-120.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
 #include "riscv_vector.h"
 
 vint16mf4_t test___riscv_vwmulsu_vx_i16mf4(vbool64_t mask, vint16mf4_t merge, vint8mf8_t op1,int8_t op2,size_t vl)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
index 2942e0b..1bca846 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/integer_compare_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
index a6df121..57d0241 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mask_insn_shortcut.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
index 276173d..9563c8d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
 #include "riscv_vector.h"
 
 vbool1_t test_vreinterpret_v_i8m1_b1 (vint8m1_t src) {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
index c1df69ac..e8b5bf8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr110109-2.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d -Wno-psabi" } */
+/* { dg-options "-O3 -march=rv32gcv -mabi=ilp32d" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
index 9c310bb..80ee1b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
index 89c96c8..d37857e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
index 484a251..d9362ec 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-msave-restore -march=rv32gc_zve64d -mabi=ilp32 -msave-restore -fno-schedule-insns -fno-schedule-insns2 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
index 5464a29..ec67357 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv32gc_zve64d -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
 #include "riscv_vector.h"
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
deleted file mode 100644
index 114ee6d..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-1.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
-  vint32m1_t a;
-  fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
deleted file mode 100644
index 0b24ccb..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-2.c
+++ /dev/null
@@ -1,15 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-/* { dg-skip-if "" { *-*-* }  { "-flto" } { "" } } */
-
-#include "riscv_vector.h"
-
-vint32m1_t
-fun (vint32m1_t* a) {  return *a; }  /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
-  vint32m1_t a;
-  fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
deleted file mode 100644
index 844a5db..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-3.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1_t*
-fun (vint32m1_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
-  vint32m1_t a;
-  fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
deleted file mode 100644
index a5dc2df..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-4.c
+++ /dev/null
@@ -1,16 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-typedef int v4si __attribute__ ((vector_size (16)));
-
-v4si
-fun (v4si a) {  return a; }  /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
-  v4si a;
-  fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
deleted file mode 100644
index 9dc6951..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-5.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-typedef int v4si __attribute__ ((vector_size (16)));
-struct A { int a; int b; };
-
-void foo (int b);
-
-void
-fun (struct A a) {
-
-        foo (a.b);
-} /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
-  struct A a;
-  fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
deleted file mode 100644
index 3a65f2c..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-6.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-#include "riscv_vector.h"
-
-void
-foo(int32_t *in1, int32_t *in2, int32_t *in3, int32_t *out,
-    size_t n, int cond) {
-  size_t vl;
-  if (cond)
-    vl = __riscv_vsetvlmax_e32m1();
-  else
-    vl = __riscv_vsetvlmax_e16mf2();
-  for (size_t i = 0; i < n; i += 1)
-    {
-      vint32m1_t a = __riscv_vle32_v_i32m1(in1, vl); /* { dg-bogus "the vector type" } */
-      vint32m1_t b = __riscv_vle32_v_i32m1_tu(a, in2, vl);
-      vint32m1_t c = __riscv_vle32_v_i32m1_tu(b, in3, vl);
-      __riscv_vse32_v_i32m1(out, c, vl);
-    }
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
deleted file mode 100644
index 2795fd4..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-7.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O0 -march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-void
-fun (vint32m1x3_t a) { } /* { dg-warning "the vector type" } */
-
-void
-bar ()
-{
-  vint32m1x3_t a;
-  fun (a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
deleted file mode 100644
index 9cf68d4..0000000
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vector-abi-8.c
+++ /dev/null
@@ -1,14 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d" } */
-
-#include "riscv_vector.h"
-
-vint32m1x3_t*
-fun (vint32m1x3_t* a) {  return a; }  /* { dg-bogus "the vector type" } */
-
-void
-bar ()
-{
-  vint32m1x3_t a;
-  fun (&a);
-}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
index 51f4fac..501d98c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include <riscv_vector.h>
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
index b27e5cc..fbcfb7b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zero_base_load_store_optimization.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
index 0e7c7cd..c951644 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-intrinsic.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
index 9ae7966..1d82cc8 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
+/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3" } */
 
 #include "riscv_vector.h"
 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
index c3519ce..be31df1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vsetvl-1.c
@@ -1,5 +1,5 @@
 /* { dg-do compile } */
-/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -Wno-psabi" } */
+/* { dg-options "--param=riscv-autovec-preference=scalable -march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
 
 #include "riscv_vector.h"