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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2023-07-26 10:07:42 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2023-07-26 15:10:53 -0600 |
| commit | aee2817ecd261ac2fd2717a2a36db81906ff2346 (patch) | |
| tree | 76f65d0e3c4a075d86cddbe6651e4cb16e178eb4 | |
| parent | 744e1f35266dbd6b6fb95c7e8422562815f8b56f (diff) | |
| download | gcc-aee2817ecd261ac2fd2717a2a36db81906ff2346.zip gcc-aee2817ecd261ac2fd2717a2a36db81906ff2346.tar.gz gcc-aee2817ecd261ac2fd2717a2a36db81906ff2346.tar.bz2 | |
[PATCH 1/5] [RISC-V] Recognize Zicond extension
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc: New extension.
* config/riscv/riscv-opts.h (MASK_ZICOND): New mask.
(TARGET_ZICOND): New target.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/attribute-20.c: New test.
* gcc.target/riscv/attribute-21.c: New test.
Co-authored-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
| -rw-r--r-- | gcc/common/config/riscv/riscv-common.cc | 3 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv-opts.h | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/attribute-20.c | 6 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/attribute-21.c | 6 |
4 files changed, 18 insertions, 0 deletions
diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 5238877..2eb8c7c 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -183,6 +183,8 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"zicond", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zawrs", ISA_SPEC_CLASS_NONE, 1, 0}, {"zba", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1316,6 +1318,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zicond", &gcc_options::x_riscv_zi_subext, MASK_ZICOND}, {"zawrs", &gcc_options::x_riscv_za_subext, MASK_ZAWRS}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index beee241..5d08993 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -238,6 +238,9 @@ enum riscv_entity #define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) #define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) +#define MASK_ZICOND (1 << 2) +#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0) + #define MASK_ZFHMIN (1 << 0) #define MASK_ZFH (1 << 1) #define MASK_ZVFHMIN (1 << 2) diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c b/gcc/testsuite/gcc.target/riscv/attribute-20.c new file mode 100644 index 0000000..b69c36c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv32i_zicond -mabi=ilp32" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv32i2p1_zicond1p0\"" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/attribute-21.c b/gcc/testsuite/gcc.target/riscv/attribute-21.c new file mode 100644 index 0000000..160312a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/attribute-21.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mriscv-attribute -march=rv64i_zicond -mabi=lp64" } */ + +void foo(){} + +/* { dg-final { scan-assembler ".attribute arch, \"rv64i2p1_zicond1p0\"" } } */ |