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| author | Jeff Law <law@redhat.com> | 2018-06-25 10:02:16 -0600 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 2018-06-25 10:02:16 -0600 |
| commit | ad111b8eb9a011d1c9c7abd92a4282d00fa1ea4f (patch) | |
| tree | 9b10d9438b4dd24e5c137cf3ab43a2d6475d057d | |
| parent | 3e85d88526441a9d936a71015f00482abcea3d9f (diff) | |
| download | gcc-ad111b8eb9a011d1c9c7abd92a4282d00fa1ea4f.zip gcc-ad111b8eb9a011d1c9c7abd92a4282d00fa1ea4f.tar.gz gcc-ad111b8eb9a011d1c9c7abd92a4282d00fa1ea4f.tar.bz2 | |
v850.md (divmodhi4): Make sure to sign extend the dividend to 32 bits.
* config/v850/v850.md (divmodhi4): Make sure to sign extend the
dividend to 32 bits. Adjust length.
(udivmodhi4): Cleanup output template. Fix length.
From-SVN: r262022
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/v850/v850.md | 12 |
2 files changed, 12 insertions, 6 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 754b5f1..ceec833 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-06-25 Jeff Law <law@redhat.com> + + * config/v850/v850.md (divmodhi4): Make sure to sign extend the + dividend to 32 bits. Adjust length. + (udivmodhi4): Cleanup output template. Fix length. + 2018-06-25 Carl Love <cel@us.ibm.com> * config/rs6000/vsx.md: Change word selector to prefered location. diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md index 2656e90..e01a310 100644 --- a/gcc/config/v850/v850.md +++ b/gcc/config/v850/v850.md @@ -738,13 +738,13 @@ (match_dup 2))) (clobber (reg:CC CC_REGNUM))] "TARGET_V850E_UP" - "divh %2,%0,%3" - [(set_attr "length" "4") + "sxh %0\n\tdivh %2,%0,%3" + [(set_attr "length" "6") (set_attr "cc" "clobber") (set_attr "type" "div")]) -;; Half-words are sign-extended by default, so we must zero extend to a word -;; here before doing the divide. +;; The half word needs to be zero/sign extended to 32 bits before doing +;; the division/modulo operation. (define_insn "udivmodhi4" [(set (match_operand:HI 0 "register_operand" "=r") @@ -755,8 +755,8 @@ (match_dup 2))) (clobber (reg:CC CC_REGNUM))] "TARGET_V850E_UP" - "zxh %0 ; divhu %2,%0,%3" - [(set_attr "length" "4") + "zxh %0\n\tdivhu %2,%0,%3" + [(set_attr "length" "6") (set_attr "cc" "clobber") (set_attr "type" "div")]) |