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| author | Jim Wilson <wilson@gcc.gnu.org> | 2019-07-08 03:47:42 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2019-07-08 03:47:42 -0700 |
| commit | ace4317affd3068cc01c06f0928e119f1559519c (patch) | |
| tree | 5e081375e6187acc9e6ffcdb8c59218a4a0b2abb | |
| parent | ce79110f01f445d97a32f93cc53c346cf98a5425 (diff) | |
| download | gcc-ace4317affd3068cc01c06f0928e119f1559519c.zip gcc-ace4317affd3068cc01c06f0928e119f1559519c.tar.gz gcc-ace4317affd3068cc01c06f0928e119f1559519c.tar.bz2 | |
RISC-V: Fix splitter for 32-bit AND on 64-bit target.
Fixes github.com/riscv/riscv-gcc issue #161. We were accidentally using
BITS_PER_WORD to compute shift counts when we should have been using the
bitsize of the operand modes. This was wrong when we had an SImode shift
and a 64-bit target.
Andrew Waterman <andrew@sifive.com>
gcc/
* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
bitsize instead of BITS_PER_WORD.
gcc/testsuite/
* gcc.target/riscv/shift-shift-2.c: Add one more test.
From-SVN: r273230
| -rw-r--r-- | gcc/ChangeLog | 7 | ||||
| -rw-r--r-- | gcc/config/riscv/riscv.md | 5 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/riscv/shift-shift-2.c | 16 |
4 files changed, 28 insertions, 4 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 31ad4e5..6429407 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-07-08 Andrew Waterman <andrew@sifive.com> + Jim Wilson <jimw@sifive.com> + + * config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1] + bitsize instead of BITS_PER_WORD. + gcc/testsuite/ + 2019-07-08 Martin Liska <mliska@suse.cz> * collect2.c (defined): Revert to before r254460. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 0f46266..78260fc 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1776,10 +1776,11 @@ (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] { - operands[2] = GEN_INT (BITS_PER_WORD + /* Op2 is a VOIDmode constant, so get the mode size from op1. */ + operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])) - exact_log2 (INTVAL (operands[2]) + 1)); }) - + ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros. This can be ;; split into two shifts. Otherwise it requires 3 instructions: li, sll, and. (define_split diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 61150ea..56f2f2c 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-07-08 Jim Wilson <jimw@sifive.com> + + * gcc.target/riscv/shift-shift-2.c: Add one more test. + 2019-07-08 Paolo Carlini <paolo.carlini@oracle.com> PR c++/65143 diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c index 3f07e77..10a5bb7 100644 --- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c @@ -25,5 +25,17 @@ sub4 (unsigned long i) { return (i << 52) >> 52; } -/* { dg-final { scan-assembler-times "slli" 4 } } */ -/* { dg-final { scan-assembler-times "srli" 4 } } */ + +unsigned int +sub5 (unsigned int i) +{ + unsigned int j; + j = i >> 24; + j = j * (1 << 24); + j = i - j; + return j; +} +/* { dg-final { scan-assembler-times "slli" 5 } } */ +/* { dg-final { scan-assembler-times "srli" 5 } } */ +/* { dg-final { scan-assembler-times "slliw" 1 } } */ +/* { dg-final { scan-assembler-times "srliw" 1 } } */ |