[GCC/ARM, 2/2] Add support for ASRL(imm), LSLL(imm) and LSRL(imm) instructions for Armv8.1-M Mainline

This patch is adding the following instructions:

ASRL (imm)
LSLL (imm)
LSRL (imm)

*** gcc/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
	and valid immediate.
	(ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
	(lshrdi3): Generate thumb2_lsrl for valid immediates.
	* config/arm/constraints.md (Pg): New.
	* config/arm/predicates.md (long_shift_imm): New.
	(arm_reg_or_long_shift_imm): Likewise.
	* config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
	(thumb2_lsll): Likewise.
	(thumb2_lsrl): New.

*** gcc/testsuite/ChangeLog ***

2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
	    Sudakshina Das  <sudi.das@arm.com>

	* gcc.target/arm/armv8_1m-shift-imm_1.c: New test.

7 files changed, 86 insertions, 6 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2dadf58..7986c68 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
+	    Sudakshina Das  <sudi.das@arm.com>
+
+	* config/arm/arm.md (ashldi3): Generate thumb2_lsll for both reg
+	and valid immediate.
+	(ashrdi3): Generate thumb2_asrl for both reg and valid immediate.
+	(lshrdi3): Generate thumb2_lsrl for valid immediates.
+	* config/arm/constraints.md (Pg): New.
+	* config/arm/predicates.md (long_shift_imm): New.
+	(arm_reg_or_long_shift_imm): Likewise.
+	* config/arm/thumb2.md (thumb2_asrl): New immediate alternative.
+	(thumb2_lsll): Likewise.
+	(thumb2_lsrl): New.
+
 2020-01-17  Mihail-Calin Ionescu  <mihail.ionescu@arm.com>
 	    Sudakshina Das  <sudi.das@arm.com>
 
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 315b04c..0454908 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -4405,8 +4405,8 @@
         operands[2] = force_reg (SImode, operands[2]);
 
       /* Armv8.1-M Mainline double shifts are not expanded.  */
-      if (REG_P (operands[2]))
-	{
+      if (arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2])))
+        {
 	  if (!reg_overlap_mentioned_p(operands[0], operands[1]))
 	    emit_insn (gen_movdi (operands[0], operands[1]));
 
@@ -4443,7 +4443,8 @@
   "TARGET_32BIT"
   "
   /* Armv8.1-M Mainline double shifts are not expanded.  */
-  if (TARGET_HAVE_MVE && REG_P (operands[2]))
+  if (TARGET_HAVE_MVE
+      && arm_reg_or_long_shift_imm (operands[2], GET_MODE (operands[2])))
     {
       if (!reg_overlap_mentioned_p(operands[0], operands[1]))
 	emit_insn (gen_movdi (operands[0], operands[1]));
@@ -4476,6 +4477,17 @@
                      (match_operand:SI 2 "reg_or_int_operand")))]
   "TARGET_32BIT"
   "
+  /* Armv8.1-M Mainline double shifts are not expanded.  */
+  if (TARGET_HAVE_MVE
+    && long_shift_imm (operands[2], GET_MODE (operands[2])))
+    {
+      if (!reg_overlap_mentioned_p(operands[0], operands[1]))
+        emit_insn (gen_movdi (operands[0], operands[1]));
+
+      emit_insn (gen_thumb2_lsrl (operands[0], operands[2]));
+      DONE;
+    }
+
   arm_emit_coreregs_64bit_shift (LSHIFTRT, operands[0], operands[1],
 				 operands[2], gen_reg_rtx (SImode),
 				 gen_reg_rtx (SImode));
diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md
index c67156a..fd120df 100644
--- a/gcc/config/arm/constraints.md
+++ b/gcc/config/arm/constraints.md
@@ -35,7 +35,7 @@
 ;;			 Dt, Dp, Dz, Tu
 ;; in Thumb-1 state: Pa, Pb, Pc, Pd, Pe
 ;; in Thumb-2 state: Ha, Pj, PJ, Ps, Pt, Pu, Pv, Pw, Px, Py, Pz
-;; in all states: Pf
+;; in all states: Pf, Pg
 
 ;; The following memory constraints have been used:
 ;; in ARM/Thumb-2 state: Uh, Ut, Uv, Uy, Un, Um, Us
@@ -188,6 +188,11 @@
 		    && !is_mm_consume (memmodel_from_int (ival))
 		    && !is_mm_release (memmodel_from_int (ival))")))
 
+(define_constraint "Pg"
+  "@internal In Thumb-2 state a constant in range 1 to 32"
+  (and (match_code "const_int")
+       (match_test "TARGET_THUMB2 && ival >= 1 && ival <= 32")))
+
 (define_constraint "Ps"
   "@internal In Thumb-2 state a constant in the range -255 to +255"
   (and (match_code "const_int")
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 8df99e6..3a3941e 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -336,6 +336,15 @@
 		              && (UINTVAL (XEXP (op, 1)) < 32)")))
        (match_test "mode == GET_MODE (op)")))
 
+;; True for Armv8.1-M Mainline long shift instructions.
+(define_predicate "long_shift_imm"
+  (match_test "satisfies_constraint_Pg (op)"))
+
+(define_predicate "arm_reg_or_long_shift_imm"
+  (ior (match_test "TARGET_THUMB2
+		    && arm_general_register_operand (op, GET_MODE (op))")
+       (match_test "satisfies_constraint_Pg (op)")))
+
 ;; True for MULT, to identify which variant of shift_operator is in use.
 (define_special_predicate "mult_operator"
   (match_code "mult"))
diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md
index a5986de..b0d3bd1 100644
--- a/gcc/config/arm/thumb2.md
+++ b/gcc/config/arm/thumb2.md
@@ -1630,7 +1630,7 @@
 (define_insn "thumb2_asrl"
   [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
 	(ashiftrt:DI (match_dup 0)
-		     (match_operand:SI 1 "arm_general_register_operand" "r")))]
+		     (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))]
   "TARGET_HAVE_MVE"
   "asrl%?\\t%Q0, %R0, %1"
   [(set_attr "predicable" "yes")])
@@ -1638,7 +1638,15 @@
 (define_insn "thumb2_lsll"
   [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
 	(ashift:DI (match_dup 0)
-		   (match_operand:SI 1 "arm_general_register_operand" "r")))]
+		   (match_operand:SI 1 "arm_reg_or_long_shift_imm" "rPg")))]
   "TARGET_HAVE_MVE"
   "lsll%?\\t%Q0, %R0, %1"
   [(set_attr "predicable" "yes")])
+
+(define_insn "thumb2_lsrl"
+  [(set (match_operand:DI 0 "arm_general_register_operand" "+r")
+	(lshiftrt:DI (match_dup 0)
+		     (match_operand:SI 1 "long_shift_imm" "Pg")))]
+  "TARGET_HAVE_MVE"
+  "lsrl%?\\t%Q0, %R0, %1"
+  [(set_attr "predicable" "yes")])
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 9de42e4..24e9475 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,6 +1,11 @@
 2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
 	    Sudakshina Das  <sudi.das@arm.com>
 
+	* gcc.target/arm/armv8_1m-shift-imm_1.c: New test.
+
+2020-01-17  Mihail-Calin Ionescu <mihail.ionescu@arm.com>
+	    Sudakshina Das  <sudi.das@arm.com>
+
 	* gcc.target/arm/armv8_1m-shift-reg_1.c: New test.
 
 2020-01-17  Jonathan Wakely  <jwakely@redhat.com>
diff --git a/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
new file mode 100644
index 0000000..5ffa376
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/armv8_1m-shift-imm-1.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.1-m.main+mve -mfloat-abi=softfp" } */
+
+long long longval1;
+long long unsigned longval2;
+
+long long int
+asrl_imm ()
+{
+ return (longval1 >> 14);
+}
+
+long long unsigned int
+lsrl_imm ()
+{
+ return (longval2 >> 14);
+}
+
+long long int
+lsll_imm (long long int longval3)
+{
+  return (longval3 << 14);
+}
+
+/* { dg-final { scan-assembler "asrl\\tr\[0-9\], r\[0-9\], #14" } } */
+/* { dg-final { scan-assembler "lsrl\\tr\[0-9\], r\[0-9\], #14" } } */
+/* { dg-final { scan-assembler "lsll\\tr\[0-9\], r\[0-9\], #14" } } */