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| author | David Edelsohn <dje.gcc@gmail.com> | 2021-11-08 11:46:47 -0500 |
|---|---|---|
| committer | David Edelsohn <dje.gcc@gmail.com> | 2021-11-08 11:46:47 -0500 |
| commit | a7dce7626a6d5247d7dda48fa36d3cdc258aae84 (patch) | |
| tree | 62c635a018b48eba99cc0795f343f022aed1e696 | |
| parent | d626fe77cdc40de0ae1651c8b94090eea73a719f (diff) | |
| download | gcc-a7dce7626a6d5247d7dda48fa36d3cdc258aae84.zip gcc-a7dce7626a6d5247d7dda48fa36d3cdc258aae84.tar.gz gcc-a7dce7626a6d5247d7dda48fa36d3cdc258aae84.tar.bz2 | |
powerpc: Fix vsx_splat_v4si_di breakage on Power8.
The vsx_splat_v4si_di pattern uses a Power8 and a Power9 instruction.
The final condition of TARGET_DIRECT_MODE_64BIT implicitly requires Power8.
The "we" constraint requires Power9, but also requires 64 bit. Because
the DImode pattern already requires 64 bit mode, this isn't horrible,
but it would be best to remove all uses of "we" constraint. The
mtvsrws instruction itself does not require 64 bit mode.
This patch reverts the previous change to fix the breakage.
gcc/ChangeLog:
* config/rs6000/vsx.md (vsx_splat_v4si_di): Revert "wa"
constraint to "we".
| -rw-r--r-- | gcc/config/rs6000/vsx.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index a97f7f2..83d6c7b 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -4578,7 +4578,7 @@ ;; allows us to use direct move to get the value in a vector register ;; so that we can use XXSPLTW (define_insn "vsx_splat_v4si_di" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa") + [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,we") (vec_duplicate:V4SI (truncate:SI (match_operand:DI 1 "gpc_reg_operand" "wa,r"))))] |