simd.exp: Skip all tests if no arm_neon_ok effective target support.

2015-05-21  Sandra Loosemore  <sandra@codesourcery.com>

	gcc/testsuite/
	* gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok
	effective target support.  If no arm_neon_hw support, do not attempt
	to execute the tests; only compile them.
	* gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run"
	and "dg-require-effective-target arm_neon_ok".
	* gcc.target/arm/simd/vextp16_1.c: Likewise.
	* gcc.target/arm/simd/vextp64_1.c: Likewise.
	* gcc.target/arm/simd/vextp8_1.c: Likewise.
	* gcc.target/arm/simd/vextQf32_1.c: Likewise.
	* gcc.target/arm/simd/vextQp16_1.c: Likewise.
	* gcc.target/arm/simd/vextQp64_1.c: Likewise.
	* gcc.target/arm/simd/vextQp8_1.c: Likewise.
	* gcc.target/arm/simd/vextQs16_1.c: Likewise.
	* gcc.target/arm/simd/vextQs32_1.c: Likewise.
	* gcc.target/arm/simd/vextQs64_1.c: Likewise.
	* gcc.target/arm/simd/vextQs8_1.c: Likewise.
	* gcc.target/arm/simd/vextQu16_1.c: Likewise.
	* gcc.target/arm/simd/vextQu32_1.c: Likewise.
	* gcc.target/arm/simd/vextQu64_1.c: Likewise.
	* gcc.target/arm/simd/vextQu8_1.c: Likewise.
	* gcc.target/arm/simd/vexts16_1.c: Likewise.
	* gcc.target/arm/simd/vexts32_1.c: Likewise.
	* gcc.target/arm/simd/vexts64_1.c: Likewise.
	* gcc.target/arm/simd/vexts8_1.c: Likewise.
	* gcc.target/arm/simd/vextu16_1.c: Likewise.
	* gcc.target/arm/simd/vextu32_1.c: Likewise.
	* gcc.target/arm/simd/vextu64_1.c: Likewise.
	* gcc.target/arm/simd/vextu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev16u8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32p16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qp16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qs16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qu16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32s16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev32u16_1.c: Likewise.
	* gcc.target/arm/simd/vrev32u8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64f32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64p16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64p8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qf32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qp16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qp8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qs8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64qu8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64s8_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u16_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u32_1.c: Likewise.
	* gcc.target/arm/simd/vrev64u8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnf32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnp16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnp8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqf32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqp16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqp8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqs8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnqu8_1.c: Likewise.
	* gcc.target/arm/simd/vtrns16_1.c: Likewise.
	* gcc.target/arm/simd/vtrns32_1.c: Likewise.
	* gcc.target/arm/simd/vtrns8_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu16_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu32_1.c: Likewise.
	* gcc.target/arm/simd/vtrnu8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpf32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpp16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpp8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqf32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqp16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqp8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqs8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpqu8_1.c: Likewise.
	* gcc.target/arm/simd/vuzps16_1.c: Likewise.
	* gcc.target/arm/simd/vuzps32_1.c: Likewise.
	* gcc.target/arm/simd/vuzps8_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu16_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu32_1.c: Likewise.
	* gcc.target/arm/simd/vuzpu8_1.c: Likewise.
	* gcc.target/arm/simd/vzipf32_1.c: Likewise.
	* gcc.target/arm/simd/vzipp16_1.c: Likewise.
	* gcc.target/arm/simd/vzipp8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqf32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqp16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqp8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqs8_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu16_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu32_1.c: Likewise.
	* gcc.target/arm/simd/vzipqu8_1.c: Likewise.
	* gcc.target/arm/simd/vzips16_1.c: Likewise.
	* gcc.target/arm/simd/vzips32_1.c: Likewise.
	* gcc.target/arm/simd/vzips8_1.c: Likewise.
	* gcc.target/arm/simd/vzipu16_1.c: Likewise.
	* gcc.target/arm/simd/vzipu32_1.c: Likewise.
	* gcc.target/arm/simd/vzipu8_1.c: Likewise.

From-SVN: r223508

116 files changed, 134 insertions, 226 deletions

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 930c4681..db20480 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,5 +1,126 @@
 2015-05-21  Sandra Loosemore  <sandra@codesourcery.com>
 
+	* gcc.target/arm/simd/simd.exp: Skip all tests if no arm_neon_ok
+	effective target support.  If no arm_neon_hw support, do not attempt
+	to execute the tests; only compile them.
+	* gcc.target/arm/simd/vextf32_1.c: Remove explicit "dg-do run"
+	and "dg-require-effective-target arm_neon_ok".
+	* gcc.target/arm/simd/vextp16_1.c: Likewise.
+	* gcc.target/arm/simd/vextp64_1.c: Likewise.
+	* gcc.target/arm/simd/vextp8_1.c: Likewise.
+	* gcc.target/arm/simd/vextQf32_1.c: Likewise.
+	* gcc.target/arm/simd/vextQp16_1.c: Likewise.
+	* gcc.target/arm/simd/vextQp64_1.c: Likewise.
+	* gcc.target/arm/simd/vextQp8_1.c: Likewise.
+	* gcc.target/arm/simd/vextQs16_1.c: Likewise.
+	* gcc.target/arm/simd/vextQs32_1.c: Likewise.
+	* gcc.target/arm/simd/vextQs64_1.c: Likewise.
+	* gcc.target/arm/simd/vextQs8_1.c: Likewise.
+	* gcc.target/arm/simd/vextQu16_1.c: Likewise.
+	* gcc.target/arm/simd/vextQu32_1.c: Likewise.
+	* gcc.target/arm/simd/vextQu64_1.c: Likewise.
+	* gcc.target/arm/simd/vextQu8_1.c: Likewise.
+	* gcc.target/arm/simd/vexts16_1.c: Likewise.
+	* gcc.target/arm/simd/vexts32_1.c: Likewise.
+	* gcc.target/arm/simd/vexts64_1.c: Likewise.
+	* gcc.target/arm/simd/vexts8_1.c: Likewise.
+	* gcc.target/arm/simd/vextu16_1.c: Likewise.
+	* gcc.target/arm/simd/vextu32_1.c: Likewise.
+	* gcc.target/arm/simd/vextu64_1.c: Likewise.
+	* gcc.target/arm/simd/vextu8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16p8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16qp8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16qs8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16qu8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16s8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev16u8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32p16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32p8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qp16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qp8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qs16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qs8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qu16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32qu8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32s16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32s8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32u16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev32u8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64f32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64p16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64p8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qf32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qp16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qp8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qs16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qs32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qs8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qu16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qu32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64qu8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64s16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64s32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64s8_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64u16_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64u32_1.c: Likewise.
+	* gcc.target/arm/simd/vrev64u8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnf32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnp16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnp8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqf32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqp16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqp8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqs16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqs32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqs8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqu16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqu32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnqu8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrns16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrns32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrns8_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnu16_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnu32_1.c: Likewise.
+	* gcc.target/arm/simd/vtrnu8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpf32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpp16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpp8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqf32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqp16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqp8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqs16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqs32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqs8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqu16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqu32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpqu8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzps16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzps32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzps8_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpu16_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpu32_1.c: Likewise.
+	* gcc.target/arm/simd/vuzpu8_1.c: Likewise.
+	* gcc.target/arm/simd/vzipf32_1.c: Likewise.
+	* gcc.target/arm/simd/vzipp16_1.c: Likewise.
+	* gcc.target/arm/simd/vzipp8_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqf32_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqp16_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqp8_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqs16_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqs32_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqs8_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqu16_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqu32_1.c: Likewise.
+	* gcc.target/arm/simd/vzipqu8_1.c: Likewise.
+	* gcc.target/arm/simd/vzips16_1.c: Likewise.
+	* gcc.target/arm/simd/vzips32_1.c: Likewise.
+	* gcc.target/arm/simd/vzips8_1.c: Likewise.
+	* gcc.target/arm/simd/vzipu16_1.c: Likewise.
+	* gcc.target/arm/simd/vzipu32_1.c: Likewise.
+	* gcc.target/arm/simd/vzipu8_1.c: Likewise.
+
+2015-05-21  Sandra Loosemore  <sandra@codesourcery.com>
+
 	* gcc.dg/vect/bb-slp-pr65935.c: Remove explicit "dg-do run".
 	* gcc.dg/vect/pr59354.c: Likewise.
 	* gcc.dg/vect/pr64252.c: Likewise.
diff --git a/gcc/testsuite/gcc.target/arm/simd/simd.exp b/gcc/testsuite/gcc.target/arm/simd/simd.exp
index 3afb537..fddf02f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/simd.exp
+++ b/gcc/testsuite/gcc.target/arm/simd/simd.exp
@@ -27,9 +27,22 @@ load_lib gcc-dg.exp
 # Initialize `dg'.
 dg-init
 
+# If the target hardware supports NEON, the default action is "run", otherwise
+# just "compile".
+global dg-do-what-default
+set save-dg-do-what-default ${dg-do-what-default}
+if {![check_effective_target_arm_neon_ok]} then {
+  return
+} elseif {[is-effective-target arm_neon_hw]} then {
+  set dg-do-what-default run
+} else {
+  set dg-do-what-default compile
+}
+
 # Main loop.
 dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cCS\]]] \
 	"" ""
 
 # All done.
+set dg-do-what-default ${save-dg-do-what-default}
 dg-finish
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
index c1da6d3..41efba0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
index adc0861..643aa2f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
index e8b688d..5cd1693 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp64_1.c
@@ -1,6 +1,5 @@
 /* Test the `vextQp64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_crypto } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
index 5f2cc53..24fe651 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
index c0d791d..702da6c 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
index ed5b210..b8dc896 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
index dbbee47..a0a28a0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
index 0ebdce3..ac905d8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
index 136f2b8..2b5bbf3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
index 66ce035..21a536a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
index ebe4abd..1f09987 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
index 432ac0a..ddc0911 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextQu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
index 99e0bad..d25a1ae 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
index 00695bf..5312fde 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
index 8783e16..2121fab 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp64_1.c
@@ -1,6 +1,5 @@
 /* Test the `vextp64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
 /* { dg-require-effective-target arm_crypto_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_crypto } */
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
index 2ba72c1..544ac03 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
index 4fa57d6..2e9e891 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
index 3cd5936..cca78e8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
index 10053a5..0737ba21 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
index 194e198..ed3f50b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vexts8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vexts8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
index f69c2bd..7d9cc51 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
index b76e383..48effc0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
index eeb0be2..b4d4f87 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu64_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu64' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
index a9d62b3..aacfb39 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vextu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vextu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O3 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
index fddb32f..7eec892 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
index b4634b8..073b7c4 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
index 691799b..9d36c7a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
index f6ab4ac..bbcf171 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
index 0a03721..f7d0f7a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
index 7e5f548..e94b708 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev16u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev16u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
index f3643fa..b3d1702 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
index d823e59..664cae8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
index f8ba8a9..0f462d0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
index 0ddf608..44f4be3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
index 30d0314..8ad01ea 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
index 03ddd2b..b049593 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
index 7176543..7c2602a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
index 403292c..0d98d19 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
index e182ab9..8642c79 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
index a48c415..37411b1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
index 076f8ab..2293f49 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
index 240d459..5d71905 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev32u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev32u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
index f5d3bca..d393baf 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64f32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64f32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
index 8c685c0..d61cdb8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
index 67ac1e4..6ac5281 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64p8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
index 74130b7..8e576a1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_f32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
index 71f3b4b..b60a005 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_p16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
index 324a738..c50ea03 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_p8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
index 9a373ec..f294c2f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
index 0f10c6c..f1c953f 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
index cf38014..42a59a0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
index 010d6db..14f5769 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
index 908769c..8ad81e8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
index 2fa07d1..f094926 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64qu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64q_u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
index f14319c..d448e48 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
index ead5722..8cfee43 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
index 29d684d..685bfa3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64s8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64s8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
index feddacc..7b87148 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
index 92a81f4..589d678 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
index f904af5..9bd14bd 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vrev64u8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vrev64u8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
index 0f9b6c9..91be871 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
index 0ff4319..695c208 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
index 2b047e4..5124f61 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
index dd4e883..bad97a5 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
index 374eee3..26a6cf4 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
index b252fd5..e883523 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
index 5f06d2a..19bbb48 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
index 221175c..348bd96 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
index 9352b37..3b60718 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
index 7f40109..e12bad1 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
index 1c61fc3..9d05120 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
index 82f911d..a59a908 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
index af2c68f..330af22 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
index 35a98ea..b20a752 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
index 395015d..ce26816 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrns8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrns8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
index df0d963..a8343ae 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
index 764ed62..7d2f36d 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
index f5b4d68..65521f9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vtrnu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vtrnu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
index 723c86a..845d203 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
index c7ad757b..0922623 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
index 670b550..916e396 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
index 53147f1..bcdf303 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
index feef15a..4d3aeab 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
index db98f35..9288c4b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
index 808d562..9c7e10e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
index 7adf5f9..60a79c9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
index 9d0256a..4757eac 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
index 23106ed..cb33d4a 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
index 0002fdf..ebaeea0 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
index f8d19dc..221cde6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
index 6e3f2eb..77ccb47 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
index 372c393..42a763b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
index 3338477..5a9242e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzps8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzps8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
index 378b5a9..b43df71 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
index ebb0d6b..0e746c8 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
index 82719a5..fbdcec7 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vuzpu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vuzpu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
index efaa96e..55cb956 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
index 4154333..7b67457 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
index 9fe2384..8222857 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
index 8c547a7..34f8afc 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqf32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQf32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
index e2af10b..f0ef7fe 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQp16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
index 11a1329..2e78311 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqp8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQp8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
index 0576c00..89ed05e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
index 6cf2439..9f4ed6e 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
index 0244374..9bb0d77 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqs8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQs8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
index 3c406f5..6a5b6a9 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
index ba1393c..e46681b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
index 023ecac..882169b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipqu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipQu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
index b6c3c2f..5c2b680 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
index 1a6f170..5deb49b 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
index 8569357..69a1b65 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzips8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzips8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
index 23bfcc4..0c47896 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu16_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu16' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
index 6a753f2..8b666a3 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu32_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu32' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */
 
diff --git a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
index 972af74..f7878a6 100644
--- a/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
+++ b/gcc/testsuite/gcc.target/arm/simd/vzipu8_1.c
@@ -1,7 +1,5 @@
 /* Test the `vzipu8' ARM Neon intrinsic.  */
 
-/* { dg-do run } */
-/* { dg-require-effective-target arm_neon_ok } */
 /* { dg-options "-save-temps -O1 -fno-inline" } */
 /* { dg-add-options arm_neon } */