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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-04-25 15:24:13 +0200 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-07-12 16:12:27 +0800 |
| commit | a3480aacc4ab01651725a63e05829a43bc23d549 (patch) | |
| tree | 8387a6975b72d1a5b248e0d1b72c4046429c35d2 | |
| parent | b621883620b127caf20e88e59fa73e666960013e (diff) | |
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riscv: Define Xmode macro
Define a Xmode macro that specifies the registers size (XLEN)
similar to Pmode. This allows the backend code to write generic
RV32/RV64 C code (under certain circumstances).
gcc/ChangeLog:
* config/riscv/riscv.h (Xmode): New macro.
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
| -rw-r--r-- | gcc/config/riscv/riscv.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 83dcac1..7d548ac 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -800,6 +800,10 @@ typedef struct { #define Pmode word_mode +/* Specify the machine mode that registers have. */ + +#define Xmode (TARGET_64BIT ? DImode : SImode) + /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */ |