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| author | Uros Bizjak <ubizjak@gmail.com> | 2016-05-13 19:27:13 +0200 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2016-05-13 19:27:13 +0200 |
| commit | a278aa17f4e95fb96762b75b8b75a6190ec95ac1 (patch) | |
| tree | 4061a59d29f5e444b0ecfcca5630493ecedf4e62 | |
| parent | 6b6435ca5c2933e729e4634f29e39215f2751f49 (diff) | |
| download | gcc-a278aa17f4e95fb96762b75b8b75a6190ec95ac1.zip gcc-a278aa17f4e95fb96762b75b8b75a6190ec95ac1.tar.gz gcc-a278aa17f4e95fb96762b75b8b75a6190ec95ac1.tar.bz2 | |
tree-vect.h (check_vect): Handle AVX2, remove XOP handling.
* gcc.dg/vect/tree-vect.h (check_vect): Handle AVX2,
remove XOP handling.
From-SVN: r236216
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.dg/vect/tree-vect.h | 17 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr61599-1.c | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr61599-2.c | 5 |
4 files changed, 19 insertions, 12 deletions
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 3e971cd..3858cd4 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2016-05-13 Uros Bizjak <ubizjak@gmail.com> + + * gcc.dg/vect/tree-vect.h (check_vect): Handle AVX2, + remove XOP handling. + 2016-05-13 Nathan Sidwell <nathan@acm.org> * gcc.dg/atomic-noinline-aux.c: Include stddef.h. Fix diff --git a/gcc/testsuite/gcc.dg/vect/tree-vect.h b/gcc/testsuite/gcc.dg/vect/tree-vect.h index 0853e3f..21bd114 100644 --- a/gcc/testsuite/gcc.dg/vect/tree-vect.h +++ b/gcc/testsuite/gcc.dg/vect/tree-vect.h @@ -32,25 +32,26 @@ check_vect (void) asm volatile (".long 0x10000484"); #elif defined(__i386__) || defined(__x86_64__) { - unsigned int a, b, c, d, want_level, want_c, want_d; + unsigned int a, b, c, d, + want_level, want_b = 0, want_c = 0, want_d = 0; /* Determine what instruction set we've been compiled for, and detect that we're running with it. This allows us to at least do a compile check for, e.g. SSE4.1 when the machine only supports SSE2. */ -# ifdef __XOP__ - want_level = 0x80000001, want_c = bit_XOP, want_d = 0; +#if defined(__AVX2__) + want_level = 7, want_b = bit_AVX2; # elif defined(__AVX__) - want_level = 1, want_c = bit_AVX, want_d = 0; + want_level = 1, want_c = bit_AVX; # elif defined(__SSE4_1__) - want_level = 1, want_c = bit_SSE4_1, want_d = 0; + want_level = 1, want_c = bit_SSE4_1; # elif defined(__SSSE3__) - want_level = 1, want_c = bit_SSSE3, want_d = 0; + want_level = 1, want_c = bit_SSSE3; # else - want_level = 1, want_c = 0, want_d = bit_SSE2; + want_level = 1, want_d = bit_SSE2; # endif if (!__get_cpuid (want_level, &a, &b, &c, &d) - || ((c & want_c) | (d & want_d)) == 0) + || ((b & want_b) | (c & want_c) | (d & want_d)) == 0) exit (0); } #elif defined(__sparc__) diff --git a/gcc/testsuite/gcc.target/i386/pr61599-1.c b/gcc/testsuite/gcc.target/i386/pr61599-1.c index 847e736..71b1c2f 100644 --- a/gcc/testsuite/gcc.target/i386/pr61599-1.c +++ b/gcc/testsuite/gcc.target/i386/pr61599-1.c @@ -1,7 +1,7 @@ /* PR target/61599 */ -/* { dg-options "-mcmodel=medium -fdata-sections" { target lp64 } } */ -/* { dg-additional-sources pr61599-2.c } */ /* { dg-do run { target lp64 } } */ +/* { dg-additional-sources pr61599-2.c } */ +/* { dg-options "-mcmodel=medium -fdata-sections" } */ char a[1*1024*1024*1024]; char b[1*1024*1024*1024]; diff --git a/gcc/testsuite/gcc.target/i386/pr61599-2.c b/gcc/testsuite/gcc.target/i386/pr61599-2.c index 22a53a4..f0d4602 100644 --- a/gcc/testsuite/gcc.target/i386/pr61599-2.c +++ b/gcc/testsuite/gcc.target/i386/pr61599-2.c @@ -1,7 +1,8 @@ /* PR target/61599 */ -/* With -mcmodel=medium, all the arrays will be treated as large data. */ -/* { dg-options "-mcmodel=medium -fdata-sections" { target lp64 } } */ /* { dg-do compile { target lp64 } } */ +/* { dg-options "-mcmodel=medium -fdata-sections" { target lp64 } } */ + +/* With -mcmodel=medium, all the arrays will be treated as large data. */ extern char a[]; extern char b[]; |