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| author | Jim Wilson <wilson@gcc.gnu.org> | 1997-04-21 10:57:09 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1997-04-21 10:57:09 -0700 |
| commit | 9ee3c6873784cc2f98e2fbdc55293dd76423aefa (patch) | |
| tree | 85b35d7eae975572a271c88a11784b4828ae9e8a | |
| parent | 079e639f76c1754f74b8e2dd3f5c88c9437e4596 (diff) | |
| download | gcc-9ee3c6873784cc2f98e2fbdc55293dd76423aefa.zip gcc-9ee3c6873784cc2f98e2fbdc55293dd76423aefa.tar.gz gcc-9ee3c6873784cc2f98e2fbdc55293dd76423aefa.tar.bz2 | |
(output_addsi3): New function. From addsi3 pattern.
From-SVN: r13952
| -rw-r--r-- | gcc/config/m68k/m68k.c | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c index f0c1714..2b3022e 100644 --- a/gcc/config/m68k/m68k.c +++ b/gcc/config/m68k/m68k.c @@ -1951,6 +1951,97 @@ find_addr_reg (addr) return addr; abort (); } + +/* Output assembler code to perform a 32 bit 3 operand add. */ + +char * +output_addsi3 (operands) + rtx *operands; +{ + if (! operands_match_p (operands[0], operands[1])) + { + if (!ADDRESS_REG_P (operands[1])) + { + rtx tmp = operands[1]; + + operands[1] = operands[2]; + operands[2] = tmp; + } + + /* These insns can result from reloads to access + stack slots over 64k from the frame pointer. */ + if (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) + return "move%.l %2,%0\\;add%.l %1,%0"; +#ifdef SGS + if (GET_CODE (operands[2]) == REG) + return "lea 0(%1,%2.l),%0"; + else + return "lea %c2(%1),%0"; +#else /* not SGS */ +#ifdef MOTOROLA + if (GET_CODE (operands[2]) == REG) + return "lea (%1,%2.l),%0"; + else + return "lea (%c2,%1),%0"; +#else /* not MOTOROLA (MIT syntax) */ + if (GET_CODE (operands[2]) == REG) + return "lea %1@(0,%2:l),%0"; + else + return "lea %1@(%c2),%0"; +#endif /* not MOTOROLA */ +#endif /* not SGS */ + } + if (GET_CODE (operands[2]) == CONST_INT) + { +#ifndef NO_ADDSUB_Q + if (INTVAL (operands[2]) > 0 + && INTVAL (operands[2]) <= 8) + return "addq%.l %2,%0"; + if (INTVAL (operands[2]) < 0 + && INTVAL (operands[2]) >= -8) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2])); + return "subq%.l %2,%0"; + } + /* On the CPU32 it is faster to use two addql instructions to + add a small integer (8 < N <= 16) to a register. + Likewise for subql. */ + if (TARGET_CPU32 && REG_P (operands[0])) + { + if (INTVAL (operands[2]) > 8 + && INTVAL (operands[2]) <= 16) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) - 8); + return "addq%.l %#8,%0\\;addq%.l %2,%0"; + } + if (INTVAL (operands[2]) < -8 + && INTVAL (operands[2]) >= -16) + { + operands[2] = gen_rtx (CONST_INT, VOIDmode, + - INTVAL (operands[2]) - 8); + return "subq%.l %#8,%0\\;subq%.l %2,%0"; + } + } +#endif + if (ADDRESS_REG_P (operands[0]) + && INTVAL (operands[2]) >= -0x8000 + && INTVAL (operands[2]) < 0x8000) + { + if (TARGET_68040) + return "add%.w %2,%0"; + else +#ifdef MOTOROLA + return "lea (%c2,%0),%0"; +#else + return "lea %0@(%c2),%0"; +#endif + } + } + return "add%.l %2,%0"; +} /* Store in cc_status the expressions that the condition codes will describe after execution of an instruction whose pattern is EXP. |