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| author | J"orn Rennecke <amylaar@cygnus.co.uk> | 1998-07-09 10:18:53 +0000 |
|---|---|---|
| committer | Joern Rennecke <amylaar@gcc.gnu.org> | 1998-07-09 11:18:53 +0100 |
| commit | 9da4652288c52297d6bbbd3d205c295f4814878e (patch) | |
| tree | a2b77cb22e0e7d3896a76edf8fb9507f23f7ae90 | |
| parent | 930176e7428909c810999ab767ac367cfc444a36 (diff) | |
| download | gcc-9da4652288c52297d6bbbd3d205c295f4814878e.zip gcc-9da4652288c52297d6bbbd3d205c295f4814878e.tar.gz gcc-9da4652288c52297d6bbbd3d205c295f4814878e.tar.bz2 | |
reload1.c (emit_reload_insns): If an output reload copies only to a secondary reload register...
* reload1.c (emit_reload_insns): If an output reload copies only
to a secondary reload register, indicate that the secondary reload
does the actual store.
From-SVN: r21034
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/reload1.c | 30 |
2 files changed, 35 insertions, 1 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index e359a9c..a373deb 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +Thu Jul 9 18:12:49 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + + * reload1.c (emit_reload_insns): If an output reload copies only + to a secondary reload register, indicate that the secondary reload + does the actual store. + Thu Jul 9 18:01:05 1998 J"orn Rennecke <amylaar@cygnus.co.uk> * reload.c (find_equiv_reg): If need_stable_sp is set, diff --git a/gcc/reload1.c b/gcc/reload1.c index b6c0d8d..b115a94 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -7085,7 +7085,35 @@ emit_reload_insns (insn) SET_HARD_REG_BIT (reg_reloaded_died, src); } if (reload_spill_index[j] >= 0) - new_spill_reg_store[reload_spill_index[j]] = p; + { + int s = reload_secondary_out_reload[j]; + rtx set = single_set (p); + /* If this reload copies only to the secondary reload + register, the secondary reload does the actual + store. */ + if (s >= 0 && set == NULL_RTX) + ; /* We can't tell what function the secondary reload + has and where the actual store to the pseudo is + made; leave new_spill_reg_store alone. */ + else if (s >= 0 + && SET_SRC (set) == reload_reg_rtx[j] + && SET_DEST (set) == reload_reg_rtx[s]) + { + /* Usually the next instruction will be the + secondary reload insn; if we can confirm + that it is, setting new_spill_reg_store to + that insn will allow an extra optimization. */ + rtx s_reg = reload_reg_rtx[s]; + rtx next = NEXT_INSN (p); + reload_out[s] = reload_out[j]; + set = single_set (next); + if (set && SET_SRC (set) == s_reg + && ! new_spill_reg_store[REGNO (s_reg)]) + new_spill_reg_store[REGNO (s_reg)] = next; + } + else + new_spill_reg_store[reload_spill_index[j]] = p; + } } } |