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| author | Jim Wilson <wilson@gcc.gnu.org> | 1993-10-05 21:06:46 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 1993-10-05 21:06:46 -0700 |
| commit | 9b3fad96a672acd1d1b7a4b194065fa8fbb2a547 (patch) | |
| tree | 4db44bebaf1f2b306ab4a3057a61d0e4ae1b4353 | |
| parent | a56e71332738952aecb6a119d4a8a8e54e907985 (diff) | |
| download | gcc-9b3fad96a672acd1d1b7a4b194065fa8fbb2a547.zip gcc-9b3fad96a672acd1d1b7a4b194065fa8fbb2a547.tar.gz gcc-9b3fad96a672acd1d1b7a4b194065fa8fbb2a547.tar.bz2 | |
(uns_small_int, uns_arith_operand): New functions.
From-SVN: r5626
| -rw-r--r-- | gcc/config/sparc/sparc.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index 9f0fb34..549fb7e 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -434,6 +434,36 @@ small_int (op, mode) return (GET_CODE (op) == CONST_INT && SMALL_INT (op)); } +/* Recognize operand values for the umul instruction. That instruction sign + extends immediate values just like all other sparc instructions, but + interprets the extended result as an unsigned number. */ + +int +uns_small_int (op, mode) + rtx op; + enum machine_mode mode; +{ +#if HOST_BITS_PER_WIDE_INT > 32 + /* All allowed constants will fit a CONST_INT. */ + return (GET_CODE (op) == CONST_INT + && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000) + || (INTVAL (op) >= 0xFFFFF000 && INTVAL (op) < 0x100000000L))); +#else + return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000) + || (GET_CODE (op) == CONST_DOUBLE + && CONST_DOUBLE_HIGH (op) == 0 + && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000)); +#endif +} + +int +uns_arith_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + return register_operand (op, mode) || uns_small_int (op, mode); +} + /* Return truth value of statement that OP is a call-clobbered register. */ int clobbered_register (op, mode) |