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| author | H.J. Lu <hjl.tools@gmail.com> | 2022-03-24 21:41:12 -0700 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2022-03-26 07:15:34 -0700 |
| commit | 99591cf43fc1da0fb72b3da02ba937ba30bd2bf2 (patch) | |
| tree | 7d830be70b0cddcc71b04ad47788631bb862658b | |
| parent | 8c8993c75309901e03418eba1d6239b9a39a43b7 (diff) | |
| download | gcc-99591cf43fc1da0fb72b3da02ba937ba30bd2bf2.zip gcc-99591cf43fc1da0fb72b3da02ba937ba30bd2bf2.tar.gz gcc-99591cf43fc1da0fb72b3da02ba937ba30bd2bf2.tar.bz2 | |
x86: Use x constraint on SSSE3 patterns with MMX operands
Since PHADDW/PHADDD/PHADDSW/PHSUBW/PHSUBD/PHSUBSW/PSIGNB/PSIGNW/PSIGND
have no AVX512 version, replace the "Yv" register constraint with the
"x" register constraint.
PR target/105052
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
Replace "Yv" with "x".
(ssse3_ph<plusminus_mnemonic>dv2si3): Likewise.
(ssse3_psign<mode>3): Likewise.
| -rw-r--r-- | gcc/config/i386/sse.md | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index a9e18d3..29802d0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -20221,12 +20221,12 @@ (set_attr "mode" "TI")]) (define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3" - [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,x") (ssse3_plusminus:V4HI (vec_select:V4HI (vec_concat:V8HI - (match_operand:V4HI 1 "register_operand" "0,0,Yv") - (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")) + (match_operand:V4HI 1 "register_operand" "0,0,x") + (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,x")) (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])) (vec_select:V4HI @@ -20308,12 +20308,12 @@ (set_attr "mode" "TI")]) (define_insn_and_split "ssse3_ph<plusminus_mnemonic>dv2si3" - [(set (match_operand:V2SI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:V2SI 0 "register_operand" "=y,x,x") (plusminus:V2SI (vec_select:V2SI (vec_concat:V4SI - (match_operand:V2SI 1 "register_operand" "0,0,Yv") - (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,Yv")) + (match_operand:V2SI 1 "register_operand" "0,0,x") + (match_operand:V2SI 2 "register_mmxmem_operand" "ym,x,x")) (parallel [(const_int 0) (const_int 2)])) (vec_select:V2SI (vec_concat:V4SI (match_dup 1) (match_dup 2)) @@ -20811,10 +20811,10 @@ (set_attr "mode" "<sseinsnmode>")]) (define_insn "ssse3_psign<mode>3" - [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,Yv") + [(set (match_operand:MMXMODEI 0 "register_operand" "=y,x,x") (unspec:MMXMODEI - [(match_operand:MMXMODEI 1 "register_operand" "0,0,Yv") - (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,Yv")] + [(match_operand:MMXMODEI 1 "register_operand" "0,0,x") + (match_operand:MMXMODEI 2 "register_mmxmem_operand" "ym,x,x")] UNSPEC_PSIGN))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3" "@ |