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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2018-10-01 11:37:33 +0200 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@gcc.gnu.org> | 2018-10-01 11:37:33 +0200 |
| commit | 97e1d32c5e6efdfac3a9d6c56e8127b958fff88f (patch) | |
| tree | 0d753e582867d408691bf7c0f6a57dfa19270fb9 | |
| parent | 796a2bb27466db5a151c06707b348cb2a705c514 (diff) | |
| download | gcc-97e1d32c5e6efdfac3a9d6c56e8127b958fff88f.zip gcc-97e1d32c5e6efdfac3a9d6c56e8127b958fff88f.tar.gz gcc-97e1d32c5e6efdfac3a9d6c56e8127b958fff88f.tar.bz2 | |
[ARC] Check for odd-even register when emitting double mac ops.
gcc/
Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/arc.md (maddsidi4_split): Don't use dmac if the
destination register is not odd-even.
(umaddsidi4_split): Likewise.
gcc/testsuite/
Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/tmac-3.c: New file.
From-SVN: r264736
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/arc/arc.md | 4 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 4 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/arc/tmac-3.c | 17 |
4 files changed, 29 insertions, 2 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7783d09..8773039 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2018-10-01 Claudiu Zissulescu <claziss@synopsys.com> + + * config/arc/arc.md (maddsidi4_split): Don't use dmac if the + destination register is not odd-even. + (umaddsidi4_split): Likewise. + 2018-10-01 Richard Biener <rguenther@suse.de> * tree-inline.c (expand_call_inline): Store origin of fn diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index 181a738..95cfa45 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -6309,7 +6309,7 @@ archs4x, archs4xd, archs4xd_slow" "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD) + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) emit_insn (gen_macd (operands[0], operands[1], operands[2])); else { @@ -6409,7 +6409,7 @@ archs4x, archs4xd, archs4xd_slow" "{ rtx acc_reg = gen_rtx_REG (DImode, ACC_REG_FIRST); emit_move_insn (acc_reg, operands[3]); - if (TARGET_PLUS_MACD) + if (TARGET_PLUS_MACD && even_register_operand (operands[0], DImode)) emit_insn (gen_macdu (operands[0], operands[1], operands[2])); else { diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 4dc292a..fe679c6 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2018-10-01 Claudiu Zissulescu <claziss@synopsys.com> + + * gcc.target/arc/tmac-3.c: New file. + 2018-09-30 Paul Thomas <pault@gcc.gnu.org> PR fortran/87359 diff --git a/gcc/testsuite/gcc.target/arc/tmac-3.c b/gcc/testsuite/gcc.target/arc/tmac-3.c new file mode 100644 index 0000000..23ef173 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/tmac-3.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=hs38 -Os" } */ + +/* The compiler will assign r1r2 as a DI register, but it doesn't fit + the macd operation, hence we need to fall back on the mac + instruction. */ +typedef long long myint64_t; + +extern int d (int, myint64_t); +int b (int c) +{ + int x = (int) d; + d (c, (myint64_t)x * 2 + 1); +} + +/* { dg-final { scan-assembler "mac\\\s+r1" } } */ |