s390.md ("*adddi3_cc", [...]): Use "nonimmediate_operand" instead of "register_operand" as predicate for "%0"...

	* config/s390/s390.md ("*adddi3_cc", "*adddi3_cconly",
	"*adddi3_cconly2", "*adddi3_64", "*adddi3_31", "adddi3",
	"*addsi3_carry1_cc", "*addsi3_carry1_cconly",
	"*addsi3_carry2_cc", "*addsi3_carry2_cconly",
	"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2", "addsi3",
	"adddf3", "*adddf3", "*adddf3_ibm",
	"addsf3", "*addsf3", "*addsf3_ibm",
	"muldi3", "mulsi3", "mulsidi3",
	"muldf3", "*muldf3", "*muldf3_ibm",
	"mulsf3", "*mulsf3", "*mulsf3_ibm",
	"*anddi3_cc", "*anddi3_cconly", "anddi3",
	"*andsi3_cc", "*andsi3_cconly", "andsi3",
	"*iordi3_cc", "*iordi3_cconly", "iordi3",
	"*iorsi3_cc", "*iorsi3_cconly", "iorsi3",
	"*xordi3_cc", "*xordi3_cconly", "xordi3",
	"*xorsi3_cc", "*xorsi3_cconly", "xorsi3"): Use "nonimmediate_operand"
	instead of "register_operand" as predicate for "%0" operand.

From-SVN: r56881

2 files changed, 67 insertions, 47 deletions

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 2300556..b352d17 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,23 @@
+2002-09-06  Ulrich Weigand  <uweigand@de.ibm.com>
+
+	* config/s390/s390.md ("*adddi3_cc", "*adddi3_cconly", 
+	"*adddi3_cconly2", "*adddi3_64", "*adddi3_31", "adddi3",
+	"*addsi3_carry1_cc", "*addsi3_carry1_cconly",	
+	"*addsi3_carry2_cc", "*addsi3_carry2_cconly",
+	"*addsi3_cc", "*addsi3_cconly", "*addsi3_cconly2", "addsi3",
+	"adddf3", "*adddf3", "*adddf3_ibm", 
+	"addsf3", "*addsf3", "*addsf3_ibm",
+	"muldi3", "mulsi3", "mulsidi3",
+	"muldf3", "*muldf3", "*muldf3_ibm",
+	"mulsf3", "*mulsf3", "*mulsf3_ibm",
+	"*anddi3_cc", "*anddi3_cconly", "anddi3",
+	"*andsi3_cc", "*andsi3_cconly", "andsi3",
+	"*iordi3_cc", "*iordi3_cconly", "iordi3",
+	"*iorsi3_cc", "*iorsi3_cconly", "iorsi3",
+	"*xordi3_cc", "*xordi3_cconly", "xordi3",
+	"*xorsi3_cc", "*xorsi3_cconly", "xorsi3"): Use "nonimmediate_operand"
+	instead of "register_operand" as predicate for "%0" operand.
+
 2002-09-06  Jakub Jelinek  <jakub@redhat.com>
 
 	* configure.in (HAVE_AS_OFFSETABLE_LO10): Use -xarch=v9
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 3e106d7..b146174 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -3082,7 +3082,7 @@
 
 (define_insn "*adddi3_cc"
   [(set (reg 33) 
-        (compare (plus:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
@@ -3096,7 +3096,7 @@
 
 (define_insn "*adddi3_cconly"
   [(set (reg 33) 
-        (compare (plus:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
@@ -3109,7 +3109,7 @@
 
 (define_insn "*adddi3_cconly2"
   [(set (reg 33) 
-        (compare (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                  (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
    (clobber (match_scratch:DI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
@@ -3121,7 +3121,7 @@
 
 (define_insn "*adddi3_64"
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-        (plus:DI (match_operand:DI 1 "register_operand" "%0,0,0")
+        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
                  (match_operand:DI 2 "general_operand" "d,K,m") ) )
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
@@ -3134,7 +3134,7 @@
 
 (define_insn_and_split "*adddi3_31"
   [(set (match_operand:DI 0 "register_operand" "=&d")
-        (plus:DI (match_operand:DI 1 "register_operand" "%0")
+        (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
                  (match_operand:DI 2 "general_operand" "dm") ) )
    (clobber (reg:CC 33))]
   "!TARGET_64BIT"
@@ -3169,7 +3169,7 @@
 (define_expand "adddi3"
   [(parallel
     [(set (match_operand:DI 0 "register_operand" "")
-          (plus:DI (match_operand:DI 1 "register_operand" "")
+          (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
                    (match_operand:DI 2 "general_operand" "")))
      (clobber (reg:CC 33))])]
   ""
@@ -3212,7 +3212,7 @@
 
 (define_insn "*addsi3_carry1_cc"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (match_dup 1)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3226,7 +3226,7 @@
 
 (define_insn "*addsi3_carry1_cconly"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (match_dup 1)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -3239,7 +3239,7 @@
 
 (define_insn "*addsi3_carry2_cc"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (match_dup 2)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3253,7 +3253,7 @@
 
 (define_insn "*addsi3_carry2_cconly"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (match_dup 2)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -3266,7 +3266,7 @@
 
 (define_insn "*addsi3_cc"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -3280,7 +3280,7 @@
 
 (define_insn "*addsi3_cconly"
   [(set (reg 33) 
-        (compare (plus:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                           (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -3293,7 +3293,7 @@
 
 (define_insn "*addsi3_cconly2"
   [(set (reg 33) 
-        (compare (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                  (neg:SI (match_operand:SI 2 "general_operand" "d,m"))))
    (clobber (match_scratch:SI 0 "=d,d"))]
   "s390_match_ccmode(insn, CCLmode)"
@@ -3325,7 +3325,7 @@
 
 (define_insn "addsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-        (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0")
+        (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                  (match_operand:SI 2 "general_operand" "d,K,m")))
    (clobber (reg:CC 33))]
   ""
@@ -3364,7 +3364,7 @@
 (define_expand "adddf3"
   [(parallel
     [(set (match_operand:DF 0 "register_operand" "=f,f")
-          (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
+          (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                    (match_operand:DF 2 "general_operand" "f,m")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
@@ -3372,7 +3372,7 @@
 
 (define_insn "*adddf3"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
+        (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:DF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
@@ -3384,7 +3384,7 @@
 
 (define_insn "*adddf3_ibm"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (plus:DF (match_operand:DF 1 "register_operand" "%0,0")
+        (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:DF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
@@ -3401,7 +3401,7 @@
 (define_expand "addsf3"
   [(parallel
     [(set (match_operand:SF 0 "register_operand" "=f,f")
-          (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
+          (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                    (match_operand:SF 2 "general_operand" "f,m")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
@@ -3409,7 +3409,7 @@
 
 (define_insn "*addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
+        (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:SF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
@@ -3421,7 +3421,7 @@
 
 (define_insn "*addsf3"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (plus:SF (match_operand:SF 1 "register_operand" "%0,0")
+        (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:SF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
@@ -3762,7 +3762,7 @@
 
 (define_insn "muldi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d,d")
-        (mult:DI (match_operand:DI 1 "register_operand" "%0,0,0")
+        (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
                  (match_operand:DI 2 "general_operand" "d,K,m")))]
   "TARGET_64BIT"
   "@
@@ -3779,7 +3779,7 @@
 
 (define_insn "mulsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d,d")
-        (mult:SI  (match_operand:SI 1 "register_operand" "%0,0,0")
+        (mult:SI  (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
                   (match_operand:SI 2 "general_operand" "d,K,m")))]
   ""
   "@
@@ -3796,7 +3796,7 @@
 
 (define_expand "mulsidi3"
   [(set (match_operand:DI 0 "register_operand" "")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" ""))
 		 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" ""))))]
   "!TARGET_64BIT"
   "
@@ -3836,7 +3836,7 @@
 (define_expand "muldf3"
   [(parallel
     [(set (match_operand:DF 0 "register_operand" "=f,f")
-          (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
+          (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                    (match_operand:DF 2 "general_operand" "f,m")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
@@ -3844,7 +3844,7 @@
 
 (define_insn "*muldf3"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
+        (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:DF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
@@ -3857,7 +3857,7 @@
 
 (define_insn "*muldf3_ibm"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
-        (mult:DF (match_operand:DF 1 "register_operand" "%0,0")
+        (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:DF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
@@ -3875,7 +3875,7 @@
 (define_expand "mulsf3"
   [(parallel
     [(set (match_operand:SF 0 "register_operand" "=f,f")
-          (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
+          (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                    (match_operand:SF 2 "general_operand" "f,m")))
      (clobber (reg:CC 33))])]
   "TARGET_HARD_FLOAT"
@@ -3883,7 +3883,7 @@
 
 (define_insn "*mulsf3"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
+        (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:SF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
@@ -3896,7 +3896,7 @@
 
 (define_insn "*mulsf3_ibm"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
-        (mult:SF (match_operand:SF 1 "register_operand" "%0,0")
+        (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
                  (match_operand:SF 2 "general_operand" "f,m")))
    (clobber (reg:CC 33))]
   "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
@@ -4395,7 +4395,7 @@
 
 (define_insn "*anddi3_cc"
   [(set (reg 33)
-        (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4409,7 +4409,7 @@
 
 (define_insn "*anddi3_cconly"
   [(set (reg 33)
-        (compare (and:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
@@ -4445,7 +4445,7 @@
 
 (define_insn "anddi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (and:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:DI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
@@ -4481,7 +4481,7 @@
 
 (define_insn "*andsi3_cc"
   [(set (reg 33)
-        (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -4495,7 +4495,7 @@
 
 (define_insn "*andsi3_cconly"
   [(set (reg 33)
-        (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -4529,7 +4529,7 @@
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (and:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:SI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   ""
@@ -4666,7 +4666,7 @@
 
 (define_insn "*iordi3_cc"
   [(set (reg 33)
-        (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4680,7 +4680,7 @@
 
 (define_insn "*iordi3_cconly"
   [(set (reg 33)
-        (compare (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
@@ -4716,7 +4716,7 @@
 
 (define_insn "iordi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (ior:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:DI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
@@ -4752,7 +4752,7 @@
 
 (define_insn "*iorsi3_cc"
   [(set (reg 33)
-        (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -4766,7 +4766,7 @@
 
 (define_insn "*iorsi3_cconly"
   [(set (reg 33)
-        (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -4800,7 +4800,7 @@
 
 (define_insn "iorsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (ior:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:SI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   ""
@@ -4937,7 +4937,7 @@
 
 (define_insn "*xordi3_cc"
   [(set (reg 33)
-        (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=d,d")
@@ -4951,7 +4951,7 @@
 
 (define_insn "*xordi3_cconly"
   [(set (reg 33)
-        (compare (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:DI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:DI 0 "=d,d"))]
@@ -4964,7 +4964,7 @@
 
 (define_insn "xordi3"
   [(set (match_operand:DI 0 "register_operand" "=d,d")
-        (xor:DI (match_operand:DI 1 "register_operand" "%0,0")
+        (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:DI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   "TARGET_64BIT"
@@ -5000,7 +5000,7 @@
 
 (define_insn "*xorsi3_cc"
   [(set (reg 33)
-        (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=d,d")
@@ -5014,7 +5014,7 @@
 
 (define_insn "*xorsi3_cconly"
   [(set (reg 33)
-        (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                          (match_operand:SI 2 "general_operand" "d,m"))
                  (const_int 0)))
    (clobber (match_scratch:SI 0 "=d,d"))]
@@ -5027,7 +5027,7 @@
 
 (define_insn "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=d,d")
-        (xor:SI (match_operand:SI 1 "register_operand" "%0,0")
+        (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
                 (match_operand:SI 2 "general_operand" "d,m")))
    (clobber (reg:CC 33))]
   ""