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| author | Richard Biener <rguenther@suse.de> | 2024-01-29 09:47:31 +0100 |
|---|---|---|
| committer | Richard Biener <rguenther@suse.de> | 2024-01-29 14:25:10 +0100 |
| commit | 96bc048d78f804bac0fa7b2ca3b6dd3a04c68217 (patch) | |
| tree | 32abbdb0c63db7366d52fe641815dfc2f63dd746 | |
| parent | d41a1873f334cf29b9a595bb03c27bff2be17319 (diff) | |
| download | gcc-96bc048d78f804bac0fa7b2ca3b6dd3a04c68217.zip gcc-96bc048d78f804bac0fa7b2ca3b6dd3a04c68217.tar.gz gcc-96bc048d78f804bac0fa7b2ca3b6dd3a04c68217.tar.bz2 | |
middle-end/113622 - allow .VEC_SET and .VEC_EXTRACT for global hard regs
The following expands .VEC_SET and .VEC_EXTRACT instruction selection
to global hard registers, not only automatic variables (possibly)
promoted to registers. This can avoid some ICEs later and create
better code.
PR middle-end/113622
* gimple-isel.cc (gimple_expand_vec_set_extract_expr):
Also allow DECL_HARD_REGISTER variables.
* gcc.target/i386/pr113622-1.c: New testcase.
| -rw-r--r-- | gcc/gimple-isel.cc | 3 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr113622-1.c | 12 |
2 files changed, 14 insertions, 1 deletions
diff --git a/gcc/gimple-isel.cc b/gcc/gimple-isel.cc index 7e2392e..54c1801 100644 --- a/gcc/gimple-isel.cc +++ b/gcc/gimple-isel.cc @@ -104,7 +104,8 @@ gimple_expand_vec_set_extract_expr (struct function *fun, machine_mode outermode = TYPE_MODE (TREE_TYPE (view_op0)); machine_mode extract_mode = TYPE_MODE (TREE_TYPE (ref)); - if (auto_var_in_fn_p (view_op0, fun->decl) + if ((auto_var_in_fn_p (view_op0, fun->decl) + || (VAR_P (view_op0) && DECL_HARD_REGISTER (view_op0))) && !TREE_ADDRESSABLE (view_op0) && ((!is_extract && can_vec_set_var_idx_p (outermode)) || (is_extract diff --git a/gcc/testsuite/gcc.target/i386/pr113622-1.c b/gcc/testsuite/gcc.target/i386/pr113622-1.c new file mode 100644 index 0000000..d3a51cd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr113622-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512f -w" } */ + +typedef float __attribute__ ((vector_size (64))) vec; +register vec a asm("zmm5"), b asm("zmm6"), c asm("zmm7"); + +void +test (void) +{ + for (int i = 0; i < 8; i++) + c[i] = a[i] < b[i] ? 0.1 : 0.2; +} |