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| author | Wilco Dijkstra <wdijkstr@arm.com> | 2016-05-16 12:52:22 +0000 |
|---|---|---|
| committer | Wilco Dijkstra <wilco@gcc.gnu.org> | 2016-05-16 12:52:22 +0000 |
| commit | 954224d7318d36379c7c997d51cc72ce1e62a7e7 (patch) | |
| tree | fdeba8af3678fe80c94540dd5ebc68408e453993 | |
| parent | e6e89f0d17162bbefd16000f65110d49a4541d41 (diff) | |
| download | gcc-954224d7318d36379c7c997d51cc72ce1e62a7e7.zip gcc-954224d7318d36379c7c997d51cc72ce1e62a7e7.tar.gz gcc-954224d7318d36379c7c997d51cc72ce1e62a7e7.tar.bz2 | |
Some patterns are using '%w2' for immediate operands...
Some patterns are using '%w2' for immediate operands, which means that a zero
immediate is actually emitted as 'wzr' or 'xzr'. This not only changes an
immediate operand into a register operand but may emit illegal instructions
from legal RTL (eg. ORR x0, SP, xzr rather than ORR x0, SP, 0).
* config/aarch64/aarch64.md
(add<mode>3_compareC_cconly_imm): Remove use of %w.
(add<mode>3_compareC_imm): Likewise.
(<optab>si3_uxtw): Split into register and immediate variants.
(andsi3_compare0_uxtw): Likewise.
(and<mode>3_compare0): Likewise.
(and<mode>3nr_compare0): Likewise.
(stack_protect_test_<mode>): Don't use %x for memory operands.
From-SVN: r236285
| -rw-r--r-- | gcc/ChangeLog | 11 | ||||
| -rw-r--r-- | gcc/config/aarch64/aarch64.md | 24 |
2 files changed, 27 insertions, 8 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 4507686..ec7cf67 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,14 @@ +2016-05-16 Wilco Dijkstra <wdijkstr@arm.com> + + * config/aarch64/aarch64.md + (add<mode>3_compareC_cconly_imm): Remove use of %w. + (add<mode>3_compareC_imm): Likewise. + (<optab>si3_uxtw): Split into register and immediate variants. + (andsi3_compare0_uxtw): Likewise. + (and<mode>3_compare0): Likewise. + (and<mode>3nr_compare0): Likewise. + (stack_protect_test_<mode>): Don't use %x for memory operands. + 2016-05-16 Matthew Fortune <matthew.fortune@imgtec.com> * config/mips/mips-cpus.def (p5600): Add multi-line brackets. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index f6bc12d..223a4cc 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -1786,7 +1786,7 @@ "aarch64_zero_extend_const_eq (<DWI>mode, operands[2], <MODE>mode, operands[1])" "@ - cmn\\t%<w>0, %<w>1 + cmn\\t%<w>0, %1 cmp\\t%<w>0, #%n1" [(set_attr "type" "alus_imm")] ) @@ -1818,11 +1818,11 @@ "aarch64_zero_extend_const_eq (<DWI>mode, operands[3], <MODE>mode, operands[2])" "@ - adds\\t%<w>0, %<w>1, %<w>2 + adds\\t%<w>0, %<w>1, %2 subs\\t%<w>0, %<w>1, #%n2" [(set_attr "type" "alus_imm")] ) - + (define_insn "add<mode>3_compareC" [(set (reg:CC_C CC_REGNUM) (ne:CC_C @@ -3425,7 +3425,9 @@ (LOGICAL:SI (match_operand:SI 1 "register_operand" "%r,r") (match_operand:SI 2 "aarch64_logical_operand" "r,K"))))] "" - "<logical>\\t%w0, %w1, %w2" + "@ + <logical>\\t%w0, %w1, %w2 + <logical>\\t%w0, %w1, %2" [(set_attr "type" "logic_reg,logic_imm")] ) @@ -3438,7 +3440,9 @@ (set (match_operand:GPI 0 "register_operand" "=r,r") (and:GPI (match_dup 1) (match_dup 2)))] "" - "ands\\t%<w>0, %<w>1, %<w>2" + "@ + ands\\t%<w>0, %<w>1, %<w>2 + ands\\t%<w>0, %<w>1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3452,7 +3456,9 @@ (set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))] "" - "ands\\t%w0, %w1, %w2" + "@ + ands\\t%w0, %w1, %w2 + ands\\t%w0, %w1, %2" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -3806,7 +3812,9 @@ (match_operand:GPI 1 "aarch64_logical_operand" "r,<lconst>")) (const_int 0)))] "" - "tst\\t%<w>0, %<w>1" + "@ + tst\\t%<w>0, %<w>1 + tst\\t%<w>0, %1" [(set_attr "type" "logics_reg,logics_imm")] ) @@ -5201,7 +5209,7 @@ UNSPEC_SP_TEST)) (clobber (match_scratch:PTR 3 "=&r"))] "" - "ldr\t%<w>3, %x1\;ldr\t%<w>0, %x2\;eor\t%<w>0, %<w>3, %<w>0" + "ldr\t%<w>3, %1\;ldr\t%<w>0, %2\;eor\t%<w>0, %<w>3, %<w>0" [(set_attr "length" "12") (set_attr "type" "multiple")]) |