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| author | Uros Bizjak <ubizjak@gmail.com> | 2020-05-14 19:51:40 +0200 |
|---|---|---|
| committer | Uros Bizjak <ubizjak@gmail.com> | 2020-05-14 19:51:40 +0200 |
| commit | 9056cd80351c65c3b9a3257644236f2007c46a3f (patch) | |
| tree | 79922706abb4cd0c42a69fdb01aed1e2aff8f9a2 | |
| parent | 098cf31aa2631db6922d4de5661c1b0ce19af0aa (diff) | |
| download | gcc-9056cd80351c65c3b9a3257644236f2007c46a3f.zip gcc-9056cd80351c65c3b9a3257644236f2007c46a3f.tar.gz gcc-9056cd80351c65c3b9a3257644236f2007c46a3f.tar.bz2 | |
i386: Add V2DFmode float trunc/extend functions [PR95046]
gcc/ChangeLog:
PR target/95046
* config/i386/sse.md (truncv2dfv2df2): New insn pattern.
(extendv2sfv2df2): Ditto.
testsuite/ChangeLog:
PR target/95046
* gcc.target/i386/pr95046-7.c: New test.
| -rw-r--r-- | gcc/ChangeLog | 6 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 33 | ||||
| -rw-r--r-- | gcc/testsuite/ChangeLog | 5 | ||||
| -rw-r--r-- | gcc/testsuite/gcc.target/i386/pr95046-7.c | 25 |
4 files changed, 69 insertions, 0 deletions
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 97e48e4..2d6b6c0 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2020-05-14 Uroš Bizjak <ubizjak@gmail.com> + + PR target/95046 + * config/i386/sse.md (truncv2dfv2df2): New insn pattern. + (extendv2sfv2df2): Ditto. + 2020-05-14 H.J. Lu <hongjiu.lu@intel.com> * configure: Regenerated. diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index dc0ecbc..28d2c43 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6504,6 +6504,25 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "V4SF")]) +(define_insn "truncv2dfv2sf2" + [(set (match_operand:V2SF 0 "register_operand" "=v") + (float_truncate:V2SF + (match_operand:V2DF 1 "vector_operand" "vBm")))] + "TARGET_MMX_WITH_SSE" +{ + if (TARGET_AVX) + return "vcvtpd2ps{x}\t{%1, %0|%0, %1}"; + else + return "cvtpd2ps\t{%1, %0|%0, %1}"; +} + [(set_attr "type" "ssecvt") + (set_attr "amdfam10_decode" "double") + (set_attr "athlon_decode" "vector") + (set_attr "bdver1_decode" "double") + (set_attr "prefix_data16" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "V4SF")]) + (define_insn "*sse2_cvtpd2ps_mask" [(set (match_operand:V4SF 0 "register_operand" "=v") (vec_concat:V4SF @@ -6664,6 +6683,20 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "V2DF")]) +(define_insn "extendv2sfv2df2" + [(set (match_operand:V2DF 0 "register_operand" "=v") + (float_extend:V2DF + (match_operand:V2SF 1 "register_operand" "v")))] + "TARGET_MMX_WITH_SSE" + "%vcvtps2pd\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "amdfam10_decode" "direct") + (set_attr "athlon_decode" "double") + (set_attr "bdver1_decode" "double") + (set_attr "prefix_data16" "0") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "V2DF")]) + (define_expand "vec_unpacks_hi_v4sf" [(set (match_dup 2) (vec_select:V4SF diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b9b968a..d82df8e 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2020-05-14 Uroš Bizjak <ubizjak@gmail.com> + + PR target/95046 + * gcc.target/i386/pr95046-7.c: New test. + 2020-05-14 Patrick Palka <ppalka@redhat.com> PR c++/78446 diff --git a/gcc/testsuite/gcc.target/i386/pr95046-7.c b/gcc/testsuite/gcc.target/i386/pr95046-7.c new file mode 100644 index 0000000..b3702a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr95046-7.c @@ -0,0 +1,25 @@ +/* PR target/95046 */ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O3 -msse2" } */ + + +float f[2]; +double d[2]; + +void +test_float_truncate (void) +{ + for (int i = 0; i < 2; i++) + f[i] = d[i]; +} + +/* { dg-final { scan-assembler "\tv?cvtpd2psx?" } } */ + +void +test_float_extend (void) +{ + for (int i = 0; i < 2; i++) + d[i] = f[i]; +} + +/* { dg-final { scan-assembler "\tv?cvtps2pd" } } */ |