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author | Vladimir N. Makarov <vmakarov@redhat.com> | 2023-06-07 09:51:54 -0400 |
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committer | Vladimir N. Makarov <vmakarov@redhat.com> | 2023-06-07 11:34:28 -0400 |
commit | 8cc8707446b77f9413654b31704f5a639673c916 (patch) | |
tree | 8f7641ca7e3bb1c0bfb2960441c9115977874766 | |
parent | b747f54a2a930da55330c2861cd1e344f67a88d9 (diff) | |
download | gcc-8cc8707446b77f9413654b31704f5a639673c916.zip gcc-8cc8707446b77f9413654b31704f5a639673c916.tar.gz gcc-8cc8707446b77f9413654b31704f5a639673c916.tar.bz2 |
RA: Constrain class of pic offset table pseudo to general regs
On some targets an integer pseudo can be assigned to a FP reg. For
pic offset table pseudo it means we will reload the pseudo in this
case and, as a consequence, memory containing the pseudo might be
recognized as wrong one. The patch fix this problem.
PR target/109541
gcc/ChangeLog:
* ira-costs.cc: (find_costs_and_classes): Constrain classes of pic
offset table pseudo to a general reg subset.
gcc/testsuite/ChangeLog:
* gcc.target/sparc/pr109541.c: New.
-rw-r--r-- | gcc/ira-costs.cc | 10 | ||||
-rw-r--r-- | gcc/testsuite/gcc.target/sparc/pr109541.c | 23 |
2 files changed, 33 insertions, 0 deletions
diff --git a/gcc/ira-costs.cc b/gcc/ira-costs.cc index ae8304f..d9e700e 100644 --- a/gcc/ira-costs.cc +++ b/gcc/ira-costs.cc @@ -2016,6 +2016,16 @@ find_costs_and_classes (FILE *dump_file) ira_assert (regno_aclass[i] != NO_REGS && ira_reg_allocno_class_p[regno_aclass[i]]); } + if (pic_offset_table_rtx != NULL + && i == (int) REGNO (pic_offset_table_rtx)) + { + /* For some targets, integer pseudos can be assigned to fp + regs. As we don't want reload pic offset table pseudo, we + should avoid using non-integer regs. */ + regno_aclass[i] + = ira_reg_class_intersect[regno_aclass[i]][GENERAL_REGS]; + alt_class = ira_reg_class_intersect[alt_class][GENERAL_REGS]; + } if ((new_class = (reg_class) (targetm.ira_change_pseudo_allocno_class (i, regno_aclass[i], best))) != regno_aclass[i]) diff --git a/gcc/testsuite/gcc.target/sparc/pr109541.c b/gcc/testsuite/gcc.target/sparc/pr109541.c new file mode 100644 index 0000000..1360f10 --- /dev/null +++ b/gcc/testsuite/gcc.target/sparc/pr109541.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-O1 -mcpu=niagara4 -fpic -w" } */ + +int rhash_sha512_process_block_A, rhash_sha512_process_block_i, +rhash_sha512_process_block_block, rhash_sha512_process_block_W_0; + +unsigned rhash_sha512_process_block_W_2; + +void rhash_sha512_process_block (void) +{ + unsigned C, E, F, G, H, W_0, W_4, W_9, W_5, W_3, T1; + + for (; rhash_sha512_process_block_i; rhash_sha512_process_block_i += 6) { + T1 = F + (rhash_sha512_process_block_W_2 += 6); + rhash_sha512_process_block_A += H & G + (W_5 += rhash_sha512_process_block_W_0); + H = C & T1 & E ^ F + (W_9 += rhash_sha512_process_block_W_0); + G = T1 ^ 6 + (W_0 += rhash_sha512_process_block_block); + F = (unsigned) &G; + T1 = (unsigned) (&T1 + (W_3 += rhash_sha512_process_block_block > 9 > W_4)); + C = (unsigned) (T1 + &E); + W_4 += W_5 += rhash_sha512_process_block_W_0; + } +} |