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| author | Jeff Law <law@gcc.gnu.org> | 1993-01-15 19:10:32 -0700 |
|---|---|---|
| committer | Jeff Law <law@gcc.gnu.org> | 1993-01-15 19:10:32 -0700 |
| commit | 85bc031ea462f57640bea340e47fa495a429b686 (patch) | |
| tree | 1de7b8bdfc7d6a67a11301abaf9da4c756f5b126 | |
| parent | f9b06ea4457c8b09f4abd72bbd0aed6fab2d4718 (diff) | |
| download | gcc-85bc031ea462f57640bea340e47fa495a429b686.zip gcc-85bc031ea462f57640bea340e47fa495a429b686.tar.gz gcc-85bc031ea462f57640bea340e47fa495a429b686.tar.bz2 | |
pa.h (LEGITIMIZE_ADDRESS): Handle (plus (mult (X) (Y)) (Z)) when Y is 2, 4, or 8 specially.
* pa.h LEGITIMIZE_ADDRESS): Handle (plus (mult (X) (Y)) (Z))
when Y is 2, 4, or 8 specially.
From-SVN: r3256
| -rw-r--r-- | gcc/config/pa/pa.h | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h index 9fe8c4f..14257e5 100644 --- a/gcc/config/pa/pa.h +++ b/gcc/config/pa/pa.h @@ -1254,7 +1254,16 @@ extern union tree_node *current_function_decl; (In the rare case of an FP register used in an integer MODE, we depend on secondary reloads and the final output pass to clean things up.) - Also change REG+(X*Y) into REG. (With X*Y in an extra pseudo). */ + + It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special + manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed + adressing modes to be used). + + Put X and Z into registers. Then put the entire expression into + a register. + + Other REG+(X*Y) addresses are placed into a register with the + X*Y subexpression placed in a register of its own. */ #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ { if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ @@ -1271,6 +1280,21 @@ extern union tree_node *current_function_decl; X = plus_constant (ptr_reg, offset & mask); \ goto WIN; \ } \ + if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT \ + && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ + && shadd_constant_p (INTVAL (XEXP (XEXP (X, 0), 1)))) \ + { \ + int val = INTVAL (XEXP (XEXP (X, 0), 1)); \ + rtx reg1, reg2; \ + reg1 = force_reg (SImode, force_operand (XEXP (X, 1), 0));\ + reg2 = force_reg (SImode, \ + force_operand (XEXP (XEXP (X, 0), 0), 0));\ + (X) = force_reg (SImode, \ + gen_rtx (PLUS, SImode, \ + gen_rtx (MULT, SImode, reg2, \ + GEN_INT (val)), \ + reg1)); \ + } \ if (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == MULT) \ (X) = force_operand (gen_rtx (PLUS, SImode, XEXP (X, 1), \ force_operand (XEXP (X, 0), 0)), 0);\ |